A method for fabricating a planarized planarization layer for an integrated circuit device is described. A barrier layer is deposited over a planarization layer. Next, a liner layer is deposited on the barrier layer. An overburden layer is deposited on the liner layer. A first chemical mechanical polishing (CMP) process is performed on the overburden layer. A surface conversion process is performed on uncovered portions of a top surface of the planarization layer which are not protected by the polished overburden layer. A first wet etch is performed of the planarization layer. In embodiments, the first wet etch is selective to metal overburden layer as compared to the planarization layer. A second wet etch is performed removing the liner layer, the diffusion barrier layer and the metal overburden layer. In embodiments, the second wet etch is selective to the planarization layer as compared to the overburden layer.

Systems and methods for shaping a film. The method of shaping a film may comprise dispensing a polymerizable fluid as a plurality of droplets onto a substrate. The method of shaping a film may further comprise bringing an initial superstrate contact region of a superstrate into contact with an initial subset of droplets of the plurality of droplets. The initial subset of droplets may merge and form an initial fluid film over the initial substrate contact region. The method of shaping a film may further comprise prior to the superstrate coming into contact with the remaining plurality of droplets on the substrate, polymerizing a region of the initial fluid film on the initial substrate contact region.

An intermediate raw material according to the present invention includes a charge control agent having a critical packing parameter of 0.6 or more and a dispersing medium and a pH of the intermediate raw material is less than 7.

Aspects of this disclosure relate to selective removal of material of a layer, such as a carbon-containing layer. The layer can be over a patterned structure of two different materials. Treating the layer to cause the removal agent to be catalytically activated by a first area of the patterned structure to remove material of the organic material over the first area at a greater rate than over a second area of the patterned structure having a different composition from the first area.

Methods for forming interconnects on a substrate with low resistivity and high dopant interfaces. In some embodiments, a method includes depositing a first copper layer with a dopant with a first dopant content of 0.5 percent to 10 percent in the interconnect by sputtering a first copper-based target at a first temperature of zero degrees Celsius to 200 degrees Celsius, annealing the substrate at a second temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the first copper layer, depositing a second copper layer with the dopant with a second dopant content of zero percent to 0.5 percent by sputtering a second copper-based target at the first temperature of zero degrees Celsius to 200 degrees Celsius, and annealing the substrate at a third temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the second copper layer.

A semiconductor component includes a substrate having an opening. The semiconductor component further includes a first dielectric liner in the opening, wherein the first dielectric liner having a thickness T.sub.1 at a first end of the opening, and a thickness T.sub.2 at a second end of the opening, and R.sub.1 is a ratio of T.sub.1 to T.sub.2. The semiconductor component further includes a second dielectric liner over the first dielectric liner, wherein the second dielectric liner having a thickness T.sub.3 at the first end of the opening, a thickness T.sub.4 at the second end of the opening, R.sub.2 is a ratio of T.sub.3 to T.sub.4, and R.sub.1 is greater than R.sub.2.

A polishing method according to the present invention, includes polishing a polishing object containing a silicon material by using a polishing composition containing abrasive grains, a tri- or more polyvalent hydroxy compound and a dispersing medium and having pH of less than 6.0.

A method is provided for producing different patterns on a single substrate. The method includes executing at least twice a sequence of the following steps: depositing a hardmask on the layer of interest and patterning the hardmask with a predefined pattern to create an accessible portion on the layer of interest; spinning a glass/carbon layer on the hardmask and on the accessible portion of the layer of interest; spin coating a block copolymer on the glass/carbon layer; transferring a predefined block copolymer pattern onto the layer of interest thereby obtaining a transferred pattern, removing the hard mask; filling the transferred pattern followed by chemical mechanical polishing or etching back, wherein different block copolymer patterns are used.

The present invention relates to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors, to a process for preparing the same, and to a process for preparing a semiconductor device using the same. The polishing pad according to an embodiment can achieve low hardness by comprising a polishing layer formed using a curing agent of specific components. It is possible to enhance the mechanical properties of the polishing pad, as well as to improve the surface defects appearing on the surface of a semiconductor substrate, by controlling the surface roughness reduction rate and the recovery elasticity index of the polishing pad to specific ranges. It is also possible to further enhance the polishing rate.

Embodiments relate to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductor devices. The polishing pad may secure excellent polishing rate and within-wafer non-uniformity by controlling the physical properties such as initial load resistivity and compressive elasticity of the cushion layer and/or the laminate as defined by Equations 1 and 2: $\begin{array}{cc}L{R}_L\left(\%\right)=\frac{T1L-T2L}{T1L-T3L}\times 100& \left[\mathrm{Equation}1\right]\\ C{E}_L\left(\%\right)=\frac{T4L-}{}\end{array}$