A method of preparing a self-aligned via on a semiconductor workpiece includes using an integrated sequence of processing steps executed on a common manufacturing platform hosting a plurality of processing modules including one or more film-forming modules, one or more etching modules, and one or more transfer modules. The integrated sequence of processing steps include receiving the workpiece into the common manufacturing platform, the workpiece having a pattern of metal features in a dielectric layer wherein exposed surfaces of the metal features and exposed surfaces of the dielectric layer together define an upper planar surface; selectively etching the metal features to form a recess pattern by recessing the exposed surfaces of the metal features beneath the exposed surfaces of the dielectric layer using one of the one or more etching modules; and depositing an etch stop layer over the recess pattern using one of the one or more film-forming modules.

The present disclosure provides a method for fabricating a semiconductor structure, including forming an inter dielectric layer over a first region and a second region of a substrate, wherein the second region is adjacent to the first region, forming a high-k material over the inter dielectric layer in the first region and the second region, forming an oxygen capturing layer over the high-k material in the first region, and applying oxidizing agent over the oxygen capturing layer.

The present disclosure provides a method for fabricating a semiconductor structure, including forming an inter dielectric layer over a first region and a second region of a substrate, wherein the second region is adjacent to the first region, forming a high-k material over the inter dielectric layer in the first region and the second region, forming an oxygen capturing layer over the high-k material in the first region, and applying oxidizing agent over the oxygen capturing layer.

A method includes forming a dummy gate structure over a wafer. Gate spacers are formed on either side of the dummy gate structure. The dummy gate structure is removed to form a gate trench between the gate spacers. A gate dielectric layer is formed in the gate trench. A gate electrode is formed over the gate dielectric layer. Forming the gate dielectric layer includes applying a first bias to the wafer. With the first bias turned on, first precursors are fed to the wafer. The first bias is turned off. After turning off the first bias, second precursors are fed to the wafer.

A method of reducing corner rounding during patterning of a substrate to form a prescribed pattern comprising a corner includes dividing the pattern into a first pattern and a second pattern, the first pattern forming a first edge of the corner and the second pattern forming a second edge of the corner. At least a portion of the second pattern overlaps the first pattern such that the first edge intersects with the second edge to form a corner of the prescribed pattern. The method further includes forming the first pattern in a first mask layer disposed on a substrate to expose the substrate and forming the second pattern in the first mask layer to expose the substrate. The substrate exposed through the first mask layer is then etched to obtain the pattern.

A method of reducing corner rounding during patterning of a substrate to form a prescribed pattern comprising a corner includes dividing the pattern into a first pattern and a second pattern, the first pattern forming a first edge of the corner and the second pattern forming a second edge of the corner. At least a portion of the second pattern overlaps the first pattern such that the first edge intersects with the second edge to form a corner of the prescribed pattern. The method further includes forming the first pattern in a first mask layer disposed on a substrate to expose the substrate and forming the second pattern in the first mask layer to expose the substrate. The substrate exposed through the first mask layer is then etched to obtain the pattern.

There is provided a technique that includes (a) supplying a fluorine-containing gas to a substrate including a first surface and a second surface; (b) supplying an oxygen- and hydrogen-containing gas and a catalyst to the substrate after performing (a); (c) supplying a modifying agent to the substrate after performing (b); and (d) supplying a film-forming agent to the substrate after performing (c).

Methods of forming patterned features on a surface of a substrate are disclosed. Exemplary methods include gas-phase formation of a layer comprising an oxalate compound on a surface of the substrate. Portions of the layer comprising the oxalate compound can be exposed to radiation or active species that form exposed and unexposed portions. Material can be selectively deposed onto the exposed or the unexposed portions.

Exemplary methods of semiconductor processing may include forming a layer of carbon-containing material on a substrate disposed within a processing region of a semiconductor processing chamber. The substrate may include an exposed region of a first dielectric material and an exposed region of a metal-containing material. The layer of carbon-containing material may be selectively formed over the exposed region of the metal-containing material. Forming the layer of carbon-containing material may include one or more cycles of providing a first molecular species that selectively couples with the metal-containing material. Forming the layer of carbon-containing material may include providing a second molecular species that selectively couples with the first molecular species. The methods may include selectively depositing a second dielectric material on the exposed region of the first dielectric material.

A method for manufacturing a semiconductor feature includes: alternatingly forming first and second dielectric layers on a semiconductor substrate along a vertical direction; forming multiple spaced-apart trenches penetrating the first and second dielectric layers; forming multiple support segments filling the trenches; removing the second dielectric layers to form multiple spaces; forming multiple conductive layers filling the spaces; removing the support segments to expose the conductive layers and the first dielectric layers; selectively forming a blocking layer covering the first dielectric layers outside of the conductive layers; forming multiple selectively-deposited sub-layers on the exposed conductive layers outside of the blocking layer and each connected to one of the conductive layers; forming multiple channel sub-layers on the selectively-deposited sub-layers outside of the blocking layer; removing the blocking layer; forming multiple isolation sub-layers filling the trenches; and forming multiple source/drain segments each connected to corresponding ones of the channel sub-layers.