A patterning method includes at least the following steps. A first material layer is provided. A second material layer is provided over the first material layer. The second material layer partially exposes the first material layer. A passivation layer is formed over the first material layer and the second material layer. A growth rate of the passivation layer on the second material layer is greater than a growth rate of the passivation layer on the first material layer. A first etching process is performed to remove a portion of the passivation layer and a portion of the first material layer.

In some embodiments, methods are provided for simultaneously and selectively depositing a first material on a first surface of a substrate and a second, different material on a second, different surface of the same substrate using the same reaction chemistries. For example, a first material may be selectively deposited on a metal surface while a second material is simultaneously and selectively deposited on an adjacent dielectric surface. The first material and the second material have different material properties, such as different etch rates.

A topology-selective deposition method is disclosed. An exemplary method includes providing an inhibition agent comprising a first nitrogen-containing gas, providing a deposition promotion agent comprising a second nitrogen-containing gas to form an activated surface on one or more of a top surface, a bottom surface, and a sidewall surface relative to one or more of the other of the top surface, the bottom surface, and the sidewall surface, and providing a precursor to react with the activated surface to thereby selectively form material comprising a nitride on the activated surface.

According to one embodiment, there is provided a substrate processing apparatus including a first electrode, a second electrode, a third electrode, a first power supply circuit, a second power supply circuit and a control line. The first electrode is arranged in a processing chamber, and on which a substrate can be placed. The second electrode faces the first electrode. The third electrode is arranged along a side wall in the processing chamber and facing the first electrode. The first power supply circuit is connected to the first electrode. The second power supply circuit is connected to the third electrode. The control line is connected to the first power supply circuit and the second power supply circuit.

According to one embodiment, there is provided a substrate processing apparatus including a first electrode, a second electrode, a third electrode, a first power supply circuit, a second power supply circuit and a control line. The first electrode is arranged in a processing chamber, and on which a substrate can be placed. The second electrode faces the first electrode. The third electrode is arranged along a side wall in the processing chamber and facing the first electrode. The first power supply circuit is connected to the first electrode. The second power supply circuit is connected to the third electrode. The control line is connected to the first power supply circuit and the second power supply circuit.

Provided is a manufacturing method for a semiconductor device including forming a first electrode layer on a front surface of a wafer, implanting, into an outer peripheral region of the front surface of the wafer, a heavy ion of an element in third and subsequent rows of a periodic table, forming an oxide film in the outer peripheral region into which the heavy ion has been implanted, and forming a second electrode layer on the first electrode layer by plating. A dose of the heavy ion may be 1E15 cm.sup.−2 or more. A depth of an implantation range of the heavy ion into the wafer may be 0.02 μm or more. The heavy ion may be an As ion, a P ion, or an Ar ion.

There is provided a film forming method of forming a film in a recess formed on a surface of a substrate. The film forming method includes: forming an adsorption-inhibiting region by supplying an adsorption-inhibiting gas to the substrate; adsorbing a silicon-containing gas to a region other than the adsorption-inhibiting region by supplying the silicon-containing gas to the substrate; and forming a silicon nitride film by exposing the substrate to a nitrogen-containing gas so that the nitrogen-containing gas reacts with the adsorbed silicon-containing gas, wherein the adsorbing the silicon-containing gas includes controlling a dose amount of the silicon-containing gas to be supplied to be equal to or greater than an adsorption saturation amount of the silicon-containing gas to be adsorbed on the substrate on which no adsorption-inhibiting region is formed.

Examples of an integrated circuit with a gate structure and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate having a channel region. A gate dielectric is formed on the channel region, and a layer containing a dopant is formed on the gate dielectric. The workpiece is annealed to transfer the dopant to the gate dielectric, and the layer is removed after the annealing. In some such examples, after the layer is removed, a work function layer is formed on the gate dielectric and a fill material is formed on the work function layer to form a gate structure.

A film formation method includes: a step of preparing a substrate including a layer of a first material formed on a surface in a first region, and a layer of a second material formed on a surface in a second region; a first SAM formation step of forming a first self-assembled monolayer in the first region by supplying a raw material gas for the first self-assembled monolayer, wherein the raw material gas corresponds to the first material; and a second SAM formation step for forming a second self-assembled monolayer including an organic acid group or a second self-assembled monolayer including a condensable group on top of the first self-assembled monolayer in the first region by supplying a first gas, which includes an organic acid group, while including a self-assembling molecule, or by supplying a second gas, which includes a condensable group, while including a self-assembling molecule.

An integrated circuit structure having a stacked transistor architecture includes a first semiconductor body (e.g., set of one or more nanoribbons) and a second semiconductor body (e.g., set of one or more nanoribbons) above the first semiconductor body. The first and second semiconductor bodies are part of the same fin structure. The distance between an upper surface of the first semiconductor body and a lower surface of the second semiconductor body is 60 nm or less. A first gate structure is on the first semiconductor body, and a second gate structure is on the second semiconductor body. An isolation structure that includes a dielectric material is between the first and second gate structures, and is on and conformal to a top surface of the first gate structure. In addition, a bottom surface of the second gate structure is on a top surface of the isolation structure, which is relatively flat.