There is provided a technique that includes: (a) supplying a molybdenumcontaining gas containing molybdenum and oxygen to a substrate in a process chamber; (b) supplying an additive gas containing hydrogen to the substrate; and (c) supplying a reducing gas containing hydrogen and having a chemical composition different from that of the additive gas to the substrate, wherein at least two of (a), (b), and (c) are performed simultaneously or to partially overlap with each other in time one or more times or (a), (b), and (c) are performed sequentially one or more times to form a molybdenum film on the substrate.

A semiconductor substrate (1) includes a front surface and a back surface opposite to each other, and a through-hole (9) penetrating from the back surface to the front surface. A metal film (10) surrounding the through-hole (9) is formed in a ring shape on the front surface. A front-surface electrode (6) includes a wiring electrode (11,12) covering the through-hole (9) and the metal film (10) and is joined to the front surface outside the metal film (10). A back-surface electrode (15) is formed on the back surface and inside the through-hole (9) and connected to the wiring electrode (11,12). The metal film (10) has a lower ionization tendency and a higher work function than the wiring electrode (11,12).

A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.

A method of depositing a material on one of two, but not both, sidewalls of a raised structure formed on a substrate includes tilting a normal of the substrate away from a source of the deposition material or tilting the source of the deposition material away from the normal of the substrate. The method may be implemented by a plasma-enhanced chemical vapor deposition (PECVD) technique.

The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.

A semiconductor device capable of improving the quality of a pixel region, an electronic apparatus including the semiconductor device, and a method for manufacturing the semiconductor device are to be provided. The present technology provides a semiconductor device that includes: a first substrate in which a pixel region including a pixel having a photoelectric conversion unit is formed; and a second substrate in which a logic circuit that processes a signal output from the pixel region is formed, the first substrate and the second substrate being stacked. In the semiconductor device, at least one of marks including a mark to be used in an exposure process during the manufacture of the semiconductor device and/or a mark to be used in an inspection process for the semiconductor device is formed in a first region that is a region between a first scribe region that is a peripheral portion of the first substrate and the pixel region and/or in a second region that is a region between a second scribe region that is a peripheral portion of the second substrate and a region corresponding to the pixel region in the second substrate.

An etching method and a plasma processing apparatus form a recess with an intended shape. The etching method includes (a) providing a substrate, the substrate including a silicon-containing film and a mask on the silicon-containing film; (b) etching the silicon-containing film with a first plasma to form a recess, the first plasma generated from a first process gas; (c) supplying a second plasma to the substrate, the second plasma generated from a second process gas comprising tungsten; and (d) etching the recess with a third plasma generated from a third process gas.

Provided is a semiconductor element capable of inspecting a plurality of wires formed in parallel. A semiconductor element according to an embodiment includes: a first circuit (45B) connected to a first position of each of a plurality of wires of a first wire group (31) including the plurality of wires; a second circuit (45A) connected to a second position corresponding to an end of each of the plurality of wires; and a plurality of connection units (43) that connects a third circuit (14) with each of the plurality of wires, the plurality of connection units (43) being provided on a one-to-one basis to the plurality of wires between the first position and the second position of each of the plurality of wires.

The present disclosure relates to a wafer, a manufacturing method thereof, and a semiconductor device. The wafer manufacturing method includes: providing a wafer having a scribe lane for die cutting. A plurality of scribe-lane through-silicon-vias is formed at the scribe lane, and the scribe-lane through-silicon-vias are filled with a protective material to form the scribe lane. Through the technique of forming through-silicon vias at the scribe lane and filling them with protective materials, performing cutting along the line of the scribe-lane through-silicon-vias during wafer scribing, the cutting stress is reduced so and damage to the die area is prevented. The scribe-lane through-silicon-vias can effectively reduce the scribe lane width, which is conducive to miniaturizing the scribe lane and improving the effective utilization of wafers.

The present invention relates to a metal interconnect structure containing no barrier metal and a method of manufacturing the metal interconnect structure. The method includes: filling at least a first interconnect trench with an intermetallic compound by depositing the intermetallic compound on an insulating layer having the first interconnect trench and a second interconnect trench formed in the insulating layer, the second interconnect trench being wider than the first interconnect trench; performing a planarization process of polishing the intermetallic compound until the insulating layer is exposed; and then performing a height adjustment process of polishing the intermetallic compound and the insulating layer until a height of the intermetallic compound in the first interconnect trench reaches a predetermined height.