In a plasma processing method for plasma etching a silicon film or polysilicon film containing boron, the polysilicon film containing boron is etched by using a mixed gas of a halogen gas, a fluorine-containing gas, and a boron trichloride gas. According to plasma processing method, it is possible to improve the etching rate and reduce etching defects when plasma etching a silicon film or polysilicon film containing boron.

A reduction in the visibility of an alignment mark of an imaging device configured by bonding a plurality of semiconductor substrates together is prevented. An imaging element includes a semiconductor substrate, a pad, an alignment mark, and a light shielding film. The semiconductor substrate includes a pixel region which is a region in which pixels for generating an image signal in accordance with incident light are disposed. The pad is disposed on a surface side of the semiconductor substrate. The alignment mark is disposed on a back surface side of the semiconductor substrate. The light shielding film is disposed between the pad and the alignment mark.

An imaging device according to an embodiment of the present disclosure includes: a first wiring layer; a first insulating film; a second insulating film; and a first electrically conducive film. The first wiring layer includes a plurality of first wiring lines extending in one direction. The first insulating film is stacked on the first wiring layer. The first insulating film forms a gap between the plurality of adjacent first wiring lines. The second insulating film is stacked on the first insulating film. The second insulating film has a planar surface. The first electrically conducive film is right opposed to at least a portion of the plurality of first wiring lines with the first insulating film and the second insulating film interposed in between.

An imaging device according to an embodiment of the present disclosure includes: a first wiring layer; a first insulating film; a second insulating film; and a first electrically conducive film. The first wiring layer includes a plurality of first wiring lines extending in one direction. The first insulating film is stacked on the first wiring layer. The first insulating film forms a gap between the plurality of adjacent first wiring lines. The second insulating film is stacked on the first insulating film. The second insulating film has a planar surface. The first electrically conducive film is right opposed to at least a portion of the plurality of first wiring lines with the first insulating film and the second insulating film interposed in between.

Nanosheets 21 to 23 are formed in line in this order in the X direction, and nanosheets 24 to 26 are formed in line in this order in the X direction. In a buried interconnect layer, a power line 11 is formed between the nanosheets 22 and 25 as viewed in plan. A face of the nanosheet 22 on a first side as one of the sides in the X direction is exposed from a gate interconnect 32. A face of the nanosheet 25 on a second side as the other side in the X direction is exposed from a gate interconnect 35.

Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include depositing a silicon-containing material on the substrate. Subsequent a first period of time, the methods may include providing a germanium-containing precursor to the processing region of the semiconductor processing chamber. The methods may include thermally reacting the silicon-containing precursor and the germanium-containing precursor at a temperature greater than or about 400° C. The methods may include forming a silicon-and-germanium-containing layer on the substrate.

A semiconductor device includes first conductive films that are provided, above a semiconductor substrate, at least on both sides of a non-formation region in which the first conductive films are not provided; an interlayer dielectric film including a first portion that is provided on the non-formation region, second portions provided above the first conductive film on both sides of the non-formation region, and a step portion that connects the first portion and the second portions; a second conductive film provided above the interlayer dielectric film; through terminal portions that penetrate the second portions of the interlayer dielectric film; and a wire bonded with the second conductive film above the first portion, where the through terminal portions include one or more first through terminal portions and one or more second through terminal portions being provided at positions opposite to each other with a bonded portion of the wire being interposed therebetween.

Provided is a solid-state imaging element, a manufacturing method, and an electronic apparatus which are capable of further improving a light-blocking effect. The solid-state imaging element has a laminated structure in which a memory substrate, a logic substrate, and a sensor substrate are laminated. The solid-state imaging element includes a through electrode that connects the memory substrate and the sensor substrate in a manner passing through a semiconductor layer of the logic substrate, and a light-blocking metal film arranged in a wiring layer included in the logic substrate and provided on the sensor substrate side, where the light-blocking metal film has an opening opened so as to allow the through electrode to pass through. The solid-state imaging element further includes a contact electrode formed on a bonded surface between the logic substrate and the sensor substrate and used to connect the through electrode to the sensor substrate side.

A semiconductor device is provided having a semiconductor substrate with a circuit layer provided on a first main surface of the semiconductor substrate. The circuit layer includes a first and second electrode layers with a dielectric layer disposed therebetween, a first outer electrode electrically connected to the first electrode layer and a second outer electrode electrically connected to the second electrode layer. When the circuit layer is viewed from above, the first electrode layer has a first facing portion facing the second electrode layer in the thickness direction and a first non-facing portion not facing the second electrode layer, and the second electrode layer has a second facing portion facing the first electrode layer in the thickness direction and a second non-facing portion not facing the first electrode layer.

The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The method of manufacturing a semiconductor device includes: providing a substrate that includes an array region and an edge region; forming a composite layer on the substrate, where the composite layer includes an amorphous silicon layer and a silicon dioxide layer, and the silicon dioxide layer is located on a surface of the amorphous silicon layer away from the substrate; dry etching the silicon dioxide layer in the array region by using first plasma, to expose a part of the surface of the amorphous silicon layer in the array region; performing, by using second plasma, a plasma surface treatment on an exposed part of the surface of the amorphous silicon layer; cleaning an amorphous silicon layer on which the plasma surface treatment has been performed and a dry etched silicon dioxide layer; and coating a first photoresist layer on the composite layer in the edge region and the array region of the substrate, and performing exposing and developing.