A technique protects a mask in plasma etching of a silicon-containing film. An etching method includes providing a substrate in a chamber included in a plasma processing apparatus. The substrate includes a silicon-containing film and a mask. The mask contains carbon. The etching method further includes etching the silicon-containing film with a chemical species in plasma generated from a process gas in the chamber. The process gas contains a halogen and phosphorus. The etching includes forming a carbon-phosphorus bond on a surface of the mask.

An apparatus for forming a film on a substrate includes: a processing container in which a reaction gas is supplied to a surface of the substrate; a stage installed in the processing container, configured to place the substrate and including a heater; a lifting shaft connected to an external lifting mechanism via a through port formed in the processing container; a casing installed between the processing container and the lifting mechanism and covering the lifting shaft; a lid member disposed to surround the lifting shaft with a gap interposed between the lifting shaft and the lid member, and installed in the processing container; a purge gas supplier configured to supply a purge gas into the casing; and a guide member disposed at a position facing the gap that opens toward an interior of the processing container and including a guide surface configured to guide the purge gas.

An electro-optical device includes a temperature detecting element and an electrostatic protection circuit configured to protect the temperature detecting element from a surge current. The electrostatic protection circuit includes a transistor electrically connected to the temperature detecting element in parallel, a first capacitance element electrically connected to the transistor, and a resistance element electrically connected to the first capacitance element in parallel. The electrostatic capacity of the first capacitance element is greater than a gate capacity between a gate electrode and a semiconductor layer that constitutes the transistor. In addition, a dielectric layer of the first capacitance element is thicker than a gate insulating film of the transistor.

An electro-optical device includes a temperature detecting element and an electrostatic protection circuit configured to protect the temperature detecting element from a surge current. The electrostatic protection circuit includes a transistor electrically connected to the temperature detecting element in parallel, a first capacitance element electrically connected to the transistor, and a resistance element electrically connected to the first capacitance element in parallel. The electrostatic capacity of the first capacitance element is greater than a gate capacity between a gate electrode and a semiconductor layer that constitutes the transistor. In addition, a dielectric layer of the first capacitance element is thicker than a gate insulating film of the transistor.

An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.

A method for fabricating a semiconductor device includes forming a stack structure including a horizontal recess over a substrate, forming a blocking layer lining the horizontal recess, forming an interface control layer including a dielectric barrier element and a conductive barrier element over the blocking layer, and forming a conductive layer over the interface control layer to fill the horizontal recess.

A manufacturing method of a metal grid includes: providing a base substrate; forming a pattern including a first dielectric layer on the base substrate through a patterning process such that the first dielectric layer has a first groove in a lattice shape; forming a second dielectric layer on a side of the first dielectric layer away from the base substrate such that the second dielectric layer is deposited at least on a sidewall of the first groove to form a second groove in a lattice shape; and forming a metal material in the second groove, and removing at least a part of a material of the second dielectric layer such that an orthographic projection of the part of the material of the second dielectric layer on the base substrate does not overlap with an orthographic projection of the metal material on the base substrate, to form a metal grid.

Molybdenum (Mo) metal-on-metal (MoM) deposition methods for providing true bottom-up fill in vias and/or other gap features in device structures. These device structures contain metal at the bottom surface and have dielectric sidewalls. The deposition process provides molybdenum growth only, in some cases, on the metal film/layer to provide a selective process that can be called a metal-on-metal (MoM) process. The Mo MoM deposition process described herein are not limited to thin films (e.g., films less than 50 Å) and can be used to deposit thicker films (e.g., greater than 50 Å in some cases and greater than 200 Å in other useful cases) on metal surfaces while no, or substantially no, deposition is found on dielectric surfaces.

Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. The semiconductor active layer and the sacrificial layer may be selectively etched in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. The capping layer and the first portion of the semiconductor active layer may be selectively etched to thereby expose the sacrificial layer. The sacrificial layer may be selectively removed from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the capping layer.

A semiconductor device according to one aspect includes a pad portion, an insulating layer that supports the pad portion, a first wiring layer that is formed in a layer below the pad portion and extends in a first direction below the pad portion, and a conductive member that is joined to a front surface of the pad portion and extends in a direction forming an angle of -30° to 30° with respect to the first direction. A semiconductor device according to another aspect includes a pad portion, an insulating layer that supports the pad portion, a first wiring layer that is formed in a layer below the pad portion and extends in a first direction below the pad portion, and a conductive member that is joined to a front surface of the pad portion and has a joint portion that is long in one direction in plan view and an angle of a long direction of the joint portion with respect to the first direction is -30° to 30°.