In one embodiment, a semiconductor storage device includes a stacked body in which a plurality of conducting layers are stacked through a plurality of insulating layers in a first direction, a semiconductor layer penetrating the stacked body, extending in the first direction and including metal atoms, and a memory film including a first insulator, a charge storage layer and a second insulator that are provided between the stacked body and the semiconductor layer. The semiconductor layer surrounds a third insulator penetrating the stacked body and extending in the first direction, and at least one crystal grain in the semiconductor layer has a shape surrounding the third insulator.

An exposure apparatus includes an illumination optical system for illuminating an original including a periodic pattern, a projection optical system for forming an image of the original on a substrate, a controller configured to cause light from the illumination optical system to be obliquely incident on the original such that a light intensity distribution which is line-symmetric with respect to a line, passing through an origin of a pupil region of the projection optical system and orthogonal to a periodic direction of the periodic pattern, is formed in the pupil region by diffracted light beams including diffracted light of not lower than 2nd-order from the periodic pattern, and to control exposure of the substrate such that each point in a shot region of the substrate is exposed in not less than two focus states.

A silicon carbide (carborundum) semiconductor device and a manufacturing method thereof. The manufacturing method of the silicon carbide semiconductor device comprises the following steps of: providing a semiconductor component structure on a silicon carbide substrate, the semiconductor component structure being formed on a front side of the silicon carbide substrate; and forming a multi-layer structure on a back side of the silicon carbide substrate, the multi-layer structure comprising a plurality of ohmic contact layers and a plurality of gettering material layers. By dispersing the gettering material into multiple layers, and by adjusting a thickness combination of the ohmic contact layer and the gettering material layer, even if the gettering material layer is relatively thin (thickness sufficient for balling), a content is still sufficient for gettering carbon and reducing carbon aggregation and accumulation.

A silicon wafer is provided in which a dopant is phosphorus, resistivity is 1.2 mΩ.Math.cm or less, and carbon concentration is 3.5×10.sup.15 atoms/cm.sup.3 or more. The carbon concentration is decreased by 10% or more near a surface of the silicon wafer compared with a center-depth of the silicon wafer.

Provided is a semiconductor device comprising a semiconductor substrate containing oxygen. An oxygen concentration distribution in a depth direction of the semiconductor substrate has a high oxygen concentration part where an oxygen concentration is higher on a further upper surface-side than a center in the depth direction of the semiconductor substrate than in a lower surface of the semiconductor substrate. The high oxygen concentration part may have a concentration peak in the oxygen concentration distribution. A crystal defect density distribution in the depth direction of the semiconductor substrate has an upper surface-side density peak on the upper surface-side of the semiconductor substrate, and the upper surface-side density peak may be arranged within a depth range in which the oxygen concentration is equal to or greater than 50% of a peak value of the concentration peak.

A semiconductor device includes a die having one or more trenches on a back side of the die. The semiconductor device also includes a layer of thermally conductive material deposited on the back side of the die to fill the one or more trenches to form one or more plated trenches. The size (e.g., surface area or thickness (Z-height)) or location of the plated trenches may be determined based on one or more heat generating elements such as logic devices (CPU or GPU, for example) on an active side of the die. The thermally conductive material, which may be a metal such as copper (Cu) or silver (Ag), has a heat dissipation coefficient that is greater than a heat dissipation coefficient of a substrate of the die.

A method of manufacturing a vertical power semiconductor device includes forming a drift region in a semiconductor body having a first main surface and a second main surface opposite to the first main surface along a vertical direction, the drift region including platinum atoms, and forming a field stop region in the semiconductor body between the drift region and the second main surface, the field stop region including a plurality of impurity peaks, wherein a first impurity peak of the plurality of impurity peaks is set a larger concentration than a second impurity peak of the plurality of impurity peaks, wherein the first impurity peak includes hydrogen and the second impurity peak includes helium.

A semiconductor structure and a method for forming a semiconductor structure are provided. A sacrificial gate layer is removed to form a gate trench exposing a sacrificial dielectric layer. An ion implantation is performed to a portion of a substrate covered by the sacrificial dielectric layer in the gate trench. The sacrificial dielectric layer is removed to expose the substrate from the gate trench. An interfacial layer is formed over the substrate in the gate trench. A metal gate structure is formed over the interfacial layer in the gate trench.

In one embodiment, a semiconductor storage device includes a stacked body in which a plurality of conducting layers are stacked through a plurality of insulating layers in a first direction, a semiconductor layer penetrating the stacked body, extending in the first direction and including metal atoms, and a memory film including a first insulator, a charge storage layer and a second insulator that are provided between the stacked body and the semiconductor layer. The semiconductor layer surrounds a third insulator penetrating the stacked body and extending in the first direction, and at least one crystal grain in the semiconductor layer has a shape surrounding the third insulator.

A method for manufacturing a carbon-doped silicon single crystal wafer, including steps of: preparing a silicon single crystal wafer not doped with carbon; performing a first RTA treatment on the silicon single crystal wafer in an atmosphere containing compound gas; performing a second RTA treatment at a higher temperature than the first RTA treatment; cooling the silicon single crystal wafer after the second RTA treatment; and performing a third RTA treatment. The crystal wafer is modified to a carbon-doped silicon single crystal wafer, sequentially from a surface thereof: a 3C-SiC single crystal layer; a carbon precipitation layer; a diffusion layer of interstitial carbon and silicon; and a diffusion layer of vacancy and carbon. A carbon-doped silicon single crystal wafer having a surface layer with high carbon concentration and uniform carbon concentration distribution to enable wafer strength enhancement; and a method for manufacturing the carbon-doped silicon single crystal wafer.