A vertical gallium oxide transistor and a preparation method thereof are provided. The method includes: annealing a gallium oxide material in an oxygen atmosphere at a range of temperature of 1000 to 1400? C. for 1 to 24 h so as to form a single crystal layer, a defective layer and an oxidized layer; removing the defective layer and the oxidized layer on a back of the gallium oxide material and the defective layer on a front of the gallium oxide material so as to obtain an initial sample; and preparing a heavily doped contact layer on the oxidized layer, preparing a source electrode layer on the contact layer, and preparing a trench perpendicular to a plane of the sample, and preparing a gate dielectric layer in the trench to fabricate a gate electrode and a drain electrode.

A vertical gallium oxide transistor and a preparation method thereof are provided. The method includes: annealing a gallium oxide material in an oxygen atmosphere at a range of temperature of 1000 to 1400? C. for 1 to 24 h so as to form a single crystal layer, a defective layer and an oxidized layer; removing the defective layer and the oxidized layer on a back of the gallium oxide material and the defective layer on a front of the gallium oxide material so as to obtain an initial sample; and preparing a heavily doped contact layer on the oxidized layer, preparing a source electrode layer on the contact layer, and preparing a trench perpendicular to a plane of the sample, and preparing a gate dielectric layer in the trench to fabricate a gate electrode and a drain electrode.

A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.

A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.

A semiconductor device with stable electrical characteristics is provided. Alternatively, a semiconductor device having normally-off electrical characteristics is provided. A semiconductor device includes a gate electrode, a gate insulator, and an oxide semiconductor, the oxide semiconductor contains fluorine in a channel formation region, and a fluorine concentration in the channel formation region is higher than or equal to 110.sup.20 atoms/cm.sup.3 and lower than or equal to 110.sup.22 atoms/cm.sup.3. Note that fluorine is added by an ion implantation method.

A semiconductor device with stable electrical characteristics is provided. Alternatively, a semiconductor device having normally-off electrical characteristics is provided. A semiconductor device includes a gate electrode, a gate insulator, and an oxide semiconductor, the oxide semiconductor contains fluorine in a channel formation region, and a fluorine concentration in the channel formation region is higher than or equal to 110.sup.20 atoms/cm.sup.3 and lower than or equal to 110.sup.22 atoms/cm.sup.3. Note that fluorine is added by an ion implantation method.

A semiconductor device according to an embodiment includes: an oxide insulating layer; an oxide semiconductor layer; a gate electrode; a gate insulating layer; and a first insulating layer, wherein the semiconductor device is divided into a first to a third regions, a thickness of the gate insulating layer in the first region is 200 nm or more, the gate electrode contacts the first insulating layer in the first region, the oxide semiconductor layer contacts the first insulating layer in the second region, an amount of impurities contained in the oxide semiconductor layer in the second region is greater than an amount of impurities contained in the oxide semiconductor layer in the first region, and an amount of impurities contained in the oxide insulating layer in the third region is greater than an amount of impurities contained in the oxide insulating layer in the second region.

A semiconductor device according to an embodiment includes: an oxide insulating layer; an oxide semiconductor layer; a gate electrode; a gate insulating layer; and a first insulating layer, wherein the semiconductor device is divided into a first to a third regions, a thickness of the gate insulating layer in the first region is 200 nm or more, the gate electrode contacts the first insulating layer in the first region, the oxide semiconductor layer contacts the first insulating layer in the second region, an amount of impurities contained in the oxide semiconductor layer in the second region is greater than an amount of impurities contained in the oxide semiconductor layer in the first region, and an amount of impurities contained in the oxide insulating layer in the third region is greater than an amount of impurities contained in the oxide insulating layer in the second region.

A thin-film transistor (TFT) and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display device are disclosed. The manufacturing method of a TFT includes: forming an active layer, a gate electrode, a source electrode and a drain electrode respectively electrically connected with the active layer, and a gate insulating layer disposed between the gate electrode and the active layer, so that the gate electrode, the source electrode and the drain electrode are formed in the same patterning process. The method can reduce the number of masks used in the manufacturing process of the TFT or an array substrate, reduce the technology process, improve the productivity, and reduce the production cost.

A thin-film transistor (TFT) and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display device are disclosed. The manufacturing method of a TFT includes: forming an active layer, a gate electrode, a source electrode and a drain electrode respectively electrically connected with the active layer, and a gate insulating layer disposed between the gate electrode and the active layer, so that the gate electrode, the source electrode and the drain electrode are formed in the same patterning process. The method can reduce the number of masks used in the manufacturing process of the TFT or an array substrate, reduce the technology process, improve the productivity, and reduce the production cost.