H01L21/425

FERROELECTRIC MEMORY DEVICE AND METHOD OF FORMING THE SAME

The present disclosure relates to an integrated chip device. The integrated chip device includes a plurality of conductive lines disposed over a substrate. The plurality of conductive lines are stacked onto one another and are separated from one another by dielectric layers interleaved between adjacent ones of the plurality of conductive lines. A ferroelectric layer is along sidewalls of the plurality of conductive lines and the dielectric layers. The ferroelectric layer separates a channel layer from the plurality of conductive lines. A species is disposed within the ferroelectric layer. The species has a concentration that decreases from the channel layer towards a surface of the ferroelectric layer that faces away from the channel layer.

Manufacturing method of semiconductor device

A manufacturing method of a semiconductor device includes: preparing a semiconductor substrate including a first semiconductor layer made of gallium oxide containing Sn and a second semiconductor layer disposed on the first semiconductor layer and made of n type gallium oxide having a Sn concentration lower than a Sn concentration of the first semiconductor layer; implanting ions of a group 2 element into the second semiconductor layer; and forming a diffusion region, in which the group 2 element diffuses, in a range from a surface of the second semiconductor layer to an interface between the second semiconductor layer and the first semiconductor layer.

Manufacturing method of semiconductor device

A manufacturing method of a semiconductor device includes: preparing a semiconductor substrate including a first semiconductor layer made of gallium oxide containing Sn and a second semiconductor layer disposed on the first semiconductor layer and made of n type gallium oxide having a Sn concentration lower than a Sn concentration of the first semiconductor layer; implanting ions of a group 2 element into the second semiconductor layer; and forming a diffusion region, in which the group 2 element diffuses, in a range from a surface of the second semiconductor layer to an interface between the second semiconductor layer and the first semiconductor layer.

Varied Component Density For Thermal Isolation
20190139742 · 2019-05-09 ·

A system that utilizes a component that controls thermal gradients and the flow of thermal energy by variation in density is disclosed. Methods of fabricating the component are also disclosed. The component is manufactured using additive manufacturing. In this way, the density of different regions of the component can be customized as desired. For example, a lattice pattern may be created in the interior of a region of the component to reduce the amount of material used. This reduces weight and also decreases the thermal conduction of that region. By using low density regions and high density regions, the flow of thermal energy can be controlled to accommodate the design constraints.

Varied Component Density For Thermal Isolation
20190139742 · 2019-05-09 ·

A system that utilizes a component that controls thermal gradients and the flow of thermal energy by variation in density is disclosed. Methods of fabricating the component are also disclosed. The component is manufactured using additive manufacturing. In this way, the density of different regions of the component can be customized as desired. For example, a lattice pattern may be created in the interior of a region of the component to reduce the amount of material used. This reduces weight and also decreases the thermal conduction of that region. By using low density regions and high density regions, the flow of thermal energy can be controlled to accommodate the design constraints.

Thin film transistor, method for manufacturing the same, and display device including the same
10283531 · 2019-05-07 · ·

Disclosed is a thin film transistor including both an N-type semiconductor layer and a P-type semiconductor layer, a method for manufacturing the same, and a display device including the same, wherein the thin film transistor may include a first gate electrode on a substrate; a first gate insulating film covering the first gate electrode; a semiconductor layer on the first gate insulating film; a second gate insulating film covering the semiconductor layer; and a second gate electrode on the second gate insulating film, wherein the semiconductor layer includes the N-type semiconductor layer and the P-type semiconductor layer.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
20190115455 · 2019-04-18 ·

A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric characteristics due to a short-channel effect is less likely to be caused. The semiconductor device includes an oxide semiconductor film having a pair of oxynitride semiconductor regions including nitrogen and an oxide semiconductor region sandwiched between the pair of oxynitride semiconductor regions, a gate insulating film, and a gate electrode provided over the oxide semiconductor region with the gate insulating film positioned therebetween. Here, the pair of oxynitride semiconductor regions serves as a source region and a drain region of the transistor, and the oxide semiconductor region serves as the channel region of the transistor.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
20190115455 · 2019-04-18 ·

A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric characteristics due to a short-channel effect is less likely to be caused. The semiconductor device includes an oxide semiconductor film having a pair of oxynitride semiconductor regions including nitrogen and an oxide semiconductor region sandwiched between the pair of oxynitride semiconductor regions, a gate insulating film, and a gate electrode provided over the oxide semiconductor region with the gate insulating film positioned therebetween. Here, the pair of oxynitride semiconductor regions serves as a source region and a drain region of the transistor, and the oxide semiconductor region serves as the channel region of the transistor.

Porous polymers for the abatement and purification of electronic gas and the removal of mercury from hydrocarbon streams

A porous material, including metal organic frameworks (MOFs) and porous organic polymer (POP), with reactivity with or sorptive affinity towards (a) electronic gas to substantially remove or abate electronic gas in an electronic gas-containing effluent, or (b) contaminants in a stream of electronic gas to substantially remove the contaminants from a stream of electronic gas and increase the purity of said electronic gas, or (c) trace mercury contaminant in a hydrocarbon stream to substantially remove said mercury contaminant and increase the purity of said hydrocarbon stream. MOFs are the coordination product of metal ions and multidentate organic ligands, whereas POPs are the product of polymerization between organic monomers.

Porous polymers for the abatement and purification of electronic gas and the removal of mercury from hydrocarbon streams

A porous material, including metal organic frameworks (MOFs) and porous organic polymer (POP), with reactivity with or sorptive affinity towards (a) electronic gas to substantially remove or abate electronic gas in an electronic gas-containing effluent, or (b) contaminants in a stream of electronic gas to substantially remove the contaminants from a stream of electronic gas and increase the purity of said electronic gas, or (c) trace mercury contaminant in a hydrocarbon stream to substantially remove said mercury contaminant and increase the purity of said hydrocarbon stream. MOFs are the coordination product of metal ions and multidentate organic ligands, whereas POPs are the product of polymerization between organic monomers.