A wedge-shaped jig (6) is inserted into a gap between a first substrate (21) and a second substrate (22) at a corner (221) of the second substrate (22) and separation of the attached first substrate (21) and second substrate (22) starts to proceed; then, a second suction pad (53) of a second suction portion (51), which is the closest to the corner (221), moves upward. Then, first suction pads (43) of first suction portions (41a), (41b), and (41c) sequentially move upward such that one side of the second substrate (22) separates from the stacked body. Although the second substrate (22) warps as the separation of the second substrate (22) proceeds, each of the plurality of first suction pads (43) elastically deforms. Therefore, the first suction pads (43) can be prevented from being detached from the second substrate (22), and the substrate (22) can be securely separated from the stacked body.

A wedge-shaped jig (6) is inserted into a gap between a first substrate (21) and a second substrate (22) at a corner (221) of the second substrate (22) and separation of the attached first substrate (21) and second substrate (22) starts to proceed; then, a second suction pad (53) of a second suction portion (51), which is the closest to the corner (221), moves upward. Then, first suction pads (43) of first suction portions (41a), (41b), and (41c) sequentially move upward such that one side of the second substrate (22) separates from the stacked body. Although the second substrate (22) warps as the separation of the second substrate (22) proceeds, each of the plurality of first suction pads (43) elastically deforms. Therefore, the first suction pads (43) can be prevented from being detached from the second substrate (22), and the substrate (22) can be securely separated from the stacked body.

A semiconductor package comprising plurality of bumps and fabricating method thereof. The package has a chip, a plurality of first and second bumps, an encapsulation, a redistribution. The chip has a plurality of pads and an active area and the active surface has a first area and a second area surrounding the first, the pads formed on a first area of the active surface, each first bump formed on the corresponding pad. The second bumps are formed on the second area, each second bump has first and second different width layers. The encapsulation encapsulates the chip and bumps and is ground to expose the bumps therefrom. During grinding, all of the first bumps are completely exposed by determining a width of an exposed surface of the second bump to electrically connect to the redistribution is increased. Therefore, a shallow-grinding or over-grinding does not occur.

A semiconductor package comprising plurality of bumps and fabricating method thereof. The package has a chip, a plurality of first and second bumps, an encapsulation, a redistribution. The chip has a plurality of pads and an active area and the active surface has a first area and a second area surrounding the first, the pads formed on a first area of the active surface, each first bump formed on the corresponding pad. The second bumps are formed on the second area, each second bump has first and second different width layers. The encapsulation encapsulates the chip and bumps and is ground to expose the bumps therefrom. During grinding, all of the first bumps are completely exposed by determining a width of an exposed surface of the second bump to electrically connect to the redistribution is increased. Therefore, a shallow-grinding or over-grinding does not occur.

Composite particles with lower mean particle size and smaller size distribution are obtained through refining treatments. The refined composite particles, such as ceria coated silica particles are used in Chemical Mechanical Planarization (CMP) compositions to offer higher removal rate; very low within wafer (WWNU) for removal rate, low dishing and low defects for polishing oxide films.

A method for preparing precise pattern of integrated circuits, which comprises the following steps: (S1) preparing a large pitch trench or circular through-hole structure with a hard mask in a first dielectric layer by lithography and etching; (S2) forming micro trench on the hard mask of the second dielectric layer at the bottom side wall of the trench or circular through-hole structure by plasma etching process; (S3) removing the first dielectric layer; (S4) opening the hard mask of the second dielectric layer at the micro trench formed on the hard mask of the second dielectric layer by plasma etching process; (S5) small pitch trench or circular through holes are prepared in the second dielectric layer.

A method for preparing precise pattern of integrated circuits, which comprises the following steps: (S1) preparing a large pitch trench or circular through-hole structure with a hard mask in a first dielectric layer by lithography and etching; (S2) forming micro trench on the hard mask of the second dielectric layer at the bottom side wall of the trench or circular through-hole structure by plasma etching process; (S3) removing the first dielectric layer; (S4) opening the hard mask of the second dielectric layer at the micro trench formed on the hard mask of the second dielectric layer by plasma etching process; (S5) small pitch trench or circular through holes are prepared in the second dielectric layer.

A method of patterning a 2D material layer is includes selectively forming a first material layer on a surface of a substrate to form a first region in which the first material layer covers the surface of the substrate and to further form a second region in which the surface of the substrate is exposed from the first material layer, the first material layer having a strong adhesive force with a 2D material. The method further includes forming a 2D material layer is formed in both the first region and the second region. The method further includes selectively removing the 2D material layer from the second region based on using a physical removal method, such that the 2D material layer remains in the first region.

A method of patterning a 2D material layer is includes selectively forming a first material layer on a surface of a substrate to form a first region in which the first material layer covers the surface of the substrate and to further form a second region in which the surface of the substrate is exposed from the first material layer, the first material layer having a strong adhesive force with a 2D material. The method further includes forming a 2D material layer is formed in both the first region and the second region. The method further includes selectively removing the 2D material layer from the second region based on using a physical removal method, such that the 2D material layer remains in the first region.

A wafer manufacturing method includes a wafer preparing step of preparing a wafer including a semiconductor device formed in each of a plurality of regions demarcated by a plurality of streets intersecting each other, a removing step of removing, from the wafer, a defective device region including a semiconductor device determined to be a defective product among a plurality of the semiconductor devices formed in the wafer, and a fitting step of fitting, into a removed region formed by removing the defective device region from the wafer, a device chip including a semiconductor device as a non-defective product having same functions as those of the semiconductor device determined to be a defective product and having a size capable of being fitted into the removed region.