A wafer manufacturing method includes a wafer preparing step of preparing a wafer including a semiconductor device formed in each of a plurality of regions demarcated by a plurality of streets intersecting each other, a removing step of removing, from the wafer, a defective device region including a semiconductor device determined to be a defective product among a plurality of the semiconductor devices formed in the wafer, and a fitting step of fitting, into a removed region formed by removing the defective device region from the wafer, a device chip including a semiconductor device as a non-defective product having same functions as those of the semiconductor device determined to be a defective product and having a size capable of being fitted into the removed region.

A spin coating method includes dispensing a coating material including a nonvolatile film material and a volatile solvent over a substrate, and spin coating the coating material over the substrate by spinning the substrate while applying ultrasound waves to the coating material to reduce a viscosity of the coating material during the spin coating.

A thin semiconductor package includes a die paddle and multiple lead fingers made of a metal substrate. A die paddle electroplating layer and a lead finger electroplating layer are formed on the surface of the die paddle and surfaces of the lead fingers, respectively. A die is provided on the die paddle electroplating layer and is electrically connected to the lead finger electroplating layer. The die paddle, the die and the lead fingers are encapsulated by a molding compound. The lower surfaces of the die paddle and the lead fingers are exposed on the bottom surface of the molding compound. The die paddles and the lead fingers are formed by etching the metal substrate instead without using a lead frame.

A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die and penetrates through the first encapsulant, and a third portion of the electron transmission path is aside the second die and penetrates through the second encapsulant.

A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die and penetrates through the first encapsulant, and a third portion of the electron transmission path is aside the second die and penetrates through the second encapsulant.

A method of manufacturing a semiconductor device includes forming a plurality of patterns of metal structures in a dielectric inorganic substrate wafer. The metal structures are accommodated in recesses of the dielectric inorganic substrate wafer and at least partly connect through the dielectric inorganic substrate. The method further includes providing a semiconductor wafer comprising a front side and a backside, wherein a plurality of electrodes is disposed on the front side of the semiconductor wafer. The front side of the semiconductor wafer is bonded to the dielectric inorganic substrate wafer to form a composite wafer, wherein the plurality of patterns of metal structures is connected to the plurality of electrodes. The composite wafer is separated into composite chips.

A method of manufacturing a semiconductor device includes forming a plurality of patterns of metal structures in a dielectric inorganic substrate wafer. The metal structures are accommodated in recesses of the dielectric inorganic substrate wafer and at least partly connect through the dielectric inorganic substrate. The method further includes providing a semiconductor wafer comprising a front side and a backside, wherein a plurality of electrodes is disposed on the front side of the semiconductor wafer. The front side of the semiconductor wafer is bonded to the dielectric inorganic substrate wafer to form a composite wafer, wherein the plurality of patterns of metal structures is connected to the plurality of electrodes. The composite wafer is separated into composite chips.

A gallium oxide substrate includes first and second main surfaces. When measured data z.sub.0(r,θ) of height differences of points (r,θ,z) on the first main surface from a least square plane of the first main surface are approximated by a function z(r,θ)=Σa.sub.nmz.sub.nm(r,θ), a ratio of a first maximum height difference of a component of z(r,θ) obtained by summing terms a.sub.nmz.sub.nm(r,θ) with an index j of 4, 9, 16, 25, 36, 49, 64, and 81, when the second main surface is placed facing a horizontal flat surface, to a diameter of the first main surface is 0.39×10.sup.−4 or less, and a ratio of a second maximum height difference of a component of z(r,θ) obtained by summing terms a.sub.nmz.sub.nm(r,θ) with j of from 4 to 81, when an entire surface of the second main surface is adsorbed to a flat chuck surface, to the diameter is 0.59×10.sup.−4 or less.

A gallium oxide substrate includes first and second main surfaces. When measured data z.sub.0(r,θ) of height differences of points (r,θ,z) on the first main surface from a least square plane of the first main surface are approximated by a function z(r,θ)=Σa.sub.nmz.sub.nm(r,θ), a ratio of a first maximum height difference of a component of z(r,θ) obtained by summing terms a.sub.nmz.sub.nm(r,θ) with an index j of 4, 9, 16, 25, 36, 49, 64, and 81, when the second main surface is placed facing a horizontal flat surface, to a diameter of the first main surface is 0.39×10.sup.−4 or less, and a ratio of a second maximum height difference of a component of z(r,θ) obtained by summing terms a.sub.nmz.sub.nm(r,θ) with j of from 4 to 81, when an entire surface of the second main surface is adsorbed to a flat chuck surface, to the diameter is 0.59×10.sup.−4 or less.

An element chip manufacturing method including: a preparing step of preparing a substrate including a plurality of element regions and a dicing region defining the element regions, the substrate having a first surface and a second surface opposite the first surface; a laser scribing step of applying a laser beam to the dicing region from a side of the first surface, to form a groove corresponding to the dicing region and being shallower than a thickness of the substrate; a cleaning step of exposing the first surface of the substrate to a first plasma, to remove debris on the groove; and a dicing step of exposing the substrate at a bottom of the groove to a second plasma after the cleaning step, to dice the substrate into element chips including the element regions. The first plasma is generated from a process gas containing a carbon oxide gas.