A thin film transistor array substrate, a method for manufacturing the same and a liquid crystal panel are provided. The film transistor array substrate has a transparent substrate formed with a gate electrode, a gate insulating layer, a semiconductor layer, an etching stop layer, a source electrode, a drain electrode, and a pixel electrode. Through using the MoTi electrode to replace the conventional ITO electrode in the film transistor array substrate, the PV layer can be simultaneously omitted in the manufacturing process of the film transistor array substrate for reducing one of the masks, lowering the manufacturing costs, and expanding the application of the IGZO structure.

A method for manufacturing an embedded chip package is provided. The method may include: forming electrically conductive lines over a substrate; placing the substrate next to a chip arrangement comprising a chip, the chip comprising one or more contact pads, wherein one or more of the electrically conductive lines are arranged proximate to a side wall of the chip; and forming one or more electrical interconnects over the chip arrangement to electrically connect at least one electrically conductive line to at least one contact pad.

Various embodiments provide a thin film transistor (TFT) device, a manufacturing method of the TFT device, and a display apparatus including the TFT device. An etch stop layer (ESL) material is formed on an active layer on a substrate. An electrical conductive layer material is formed on the ESL material for forming a source electrode and a drain electrode. The electrical conductive layer material is patterned to form a first portion of the source electrode containing a first via-hole through the source electrode, and to form a first portion of the drain electrode containing a second via-hole through the drain electrode. The ESL material is patterned to form an etch stop layer (ESL) pattern including a first ESL via-hole connecting to the first via-hole through the source electrode and including a second ESL via-hole connecting to the second via-hole through the drain electrode.

An integrated circuit with a thick TiN metal gate with a work function greater than 4.85 eV and with a thin TiN metal gate with a work function less than 4.25 eV. An integrated circuit with a replacement gate PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a replacement gate NMOS TiN metal gate transistor with a workfunction less than 4.25 eV. An integrated circuit with a gate first PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a gate first NMOS TiN metal gate transistor with a workfunction less than 4.25 eV.

A thin film transistor includes a gate electrode, a semiconductor layer, a source electrode, and a drain electrode. The semiconductor layer overlaps the gate electrode and includes a channel layer comprising an oxide semiconductor and an auxiliary layer comprising amorphous silicon. The source electrode and the drain electrode are separated from each other and connected to the semiconductor layer. A thin film transistor array panel and method of manufacturing same also is disclosed.

Methods and apparatus are disclosed for manufacturing metal contacts under ground-up contact pads within a device. A device may comprise a bottom metal layer with a bottom metal contact, a top metal layer with a top metal contact, and a plurality of middle metal layers. Any given metal layer of the plurality of middle metal layers comprises a metal contact, the metal contact is substantially vertically below the top metal contact, substantially vertically above the bottom metal contact, and substantially vertically above a metal contact in any metal layer that is below the given metal layer. The metal contacts may be of various and different shapes. All the metal contacts in the plurality of middle metal layers and the bottom metal contact may be smaller than the top metal contact, therefore occupying less area and saving more area for other functions such as device routing.

Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.

A semiconductor device includes a substrate, a gate electrode on the substrate, an insulating layer on the gate electrode, first and second lower vias in the insulating layer, first and second lower metal lines provided on the insulating layer and respectively connected to the first and second lower vias, and first and second upper metal lines provided on and respectively connected to the first and second lower metal lines. When viewed in a plan view, the first lower via is overlapped with the second upper metal line, and the second lower via is overlapped with the first upper metal line.

Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.

A flip-chip mounting technique with high reliability is provided in flip-chip mounting using a Cu pillar. In a semiconductor device to be coupled to a mounting board via a Cu pillar, the Cu pillar is caused to have a laminated structure including a pillar layer, a barrier layer, and a bump in this order from below, and the bump is formed to be smaller than the barrier layer.