The present invention provides an etchant less causing damage to IGZOs. The etchant of the present invention comprises hydroxyethanediphosphonic acid (A), one or more phosphonic acids (B), hydrogen peroxide (C), nitric acid (D), a fluorine compound (E), an azole (F), and an alkali (G), and is characterized in that the phosphoric acids (B) comprise one or more phosphonic acids selected from the group consisting of diethylenetriaminepentamethylenephosphonic acid, N,N,N′,N′-ethylenediaminetetrakismethylenephosphonic acid, and aminotrimethylenephosphonic acid and that the proportion of the hydroxyethanediphosphonic acid (A) is in the range of 0.01-0.1 mass % and the proportion of the phosphonic acids (B) is in the range of 0.003-0.04 mass %.

A thin film transistor, a manufacturing method thereof, an array substrate, and a display panel are provided. The thin film transistor includes a semiconductor layer, a source and a drain. The semiconductor layer includes an active layer and a superhydrophobic layer. The active layer includes a source contact, a drain contact and a channel portion. The source corresponds to the source contact, and the drain corresponds to the drain contact. The superhydrophobic layer is disposed on a surface of the active layer proximal to the source and the drain. The superhydrophobic layer includes a plurality of multi-level nanostructures protruding from the surface of the active layer, and the superhydrophobic layer at least covers a channel portion of the active layer.

A method including followings is provided. An encapsulated device including a semiconductor die and an insulating encapsulation laterally encapsulating the semiconductor die is provided. An insulating layer is formed over a surface of the encapsulated device. A groove pattern is formed on the insulating layer. A conductive paste is filled in the groove pattern and the conductive paste filled in the groove pattern is cured.

A method includes loading a wafer into a processing chamber, wherein the processing chamber is wound by a coil, and the coil is coupled to an RF system; supplying an aromatic hydrocarbon precursor into the processing chamber; after supplying the aromatic hydrocarbon precursor, turning on an RF power of the RF system to decompose the aromatic hydrocarbon precursor into active radicals and cyclize the active radicals into a graphene layer over a metal layer on the wafer; and after an entirety of the metal layer being covered by the graphene layer, turning off the RF power of the RF system to stop forming the graphene layer.

A manufacturing method of a display substrate, a display substrate, and a display device. The manufacturing method includes: forming an active layer; forming a gate insulation film layer, a gate film layer and a photoresist film layer; exposing the photoresist film layer to a light and developing the exposed photoresist film layer until the developed photoresist film layer has a thickness of 1.8-2.2 μm and a slope angle not less than 70°; over-etching the gate film layer to form a gate electrode, an orthographic projection of the gate electrode being located within a region of an orthographic projection of the developed photoresist film layer; over-etching the gate insulation film layer by a gaseous corrosion method to form a gate insulation layer; peeling off the photoresist film layer remaining on a surface of the gate electrode; and performing a conductive treatment to the active layer.

A semiconductor device includes thin film transistors each having an oxide semiconductor. The oxide semiconductor has a channel region, a drain region, a source region, and low concentration regions which are lower in impurity concentration than the drain region and the source region. The low concentration regions are located between the channel region and the drain region, and between the channel region and the source region. Each of the thin film transistors has a gate insulating film on the channel region and the low concentration regions, an aluminum oxide film on a first part of the gate insulating film, the first part being located on the channel region, and a gate electrode on the aluminum oxide film and a second part of the gate insulating film, the second part being located on the low concentration regions.

Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

Some embodiments relate to a semiconductor device manufacturing process. In the process, a substrate is provided, and a sacrificial layer is formed over the substrate. An opening is patterned through the sacrificial layer, and the opening is filled with conductive material. The sacrificial layer is removed while the conductive material is left in place. A first dielectric layer is formed along sidewalls of the conductive material that was left in place.

A component carrier with a stack including at least one electrically insulating layer structure and at least one electrically insulating structure has a tapering blind hole formed in the stack and an electrically conductive plating layer extending along at least part of a horizontal surface of the stack outside of the blind hole and along at least part of a surface of the blind hole. A minimum thickness of the plating layer at a bottom of the blind hole is at least 8 μm.

The present disclosure relates to a thin film transistor and a manufacturing method thereof, a flexible display screen and a display device. The thin film transistor is disposed on a substrate. The thin film transistor includes: an active layer, a source-drain conductive layer, and a gate conductive layer. The gate conductive layer includes a gate electrode, and the gate conductive layer is disposed on one side of the active layer away from the substrate and insulated from the active layer. The source-drain conductive layer includes a first electrode and a second electrode. The orthogonal projections of the first electrode, the gate electrode, and the second electrode on the substrate are sequentially nested from inside to outside and separately disposed. The reliability of image display may be improved.