A semiconductor package includes: a lead frame that includes a first surface and a second surface opposite to the first surface, where the lead frame includes a first lead that extends in a first direction, and a plurality of second leads that are spaced apart from the first lead on both sides of the first lead; at least one semiconductor chip mounted on the first surface of the lead frame by a plurality of bumps; and an encapsulant that encapsulates the lead frame and the at least one semiconductor chip, wherein the first lead has a groove in the first surface that partitions the plurality of bumps in contact with the first lead.

In one example, a semiconductor device comprises a substrate and an electronic device on a top side of the substrate, a lead frame on the top side of the substrate over the electronic device, wherein the lead frame comprises a connection bar and a lead, a component mounted to the connection bar and the lead on a top side of the lead frame, and an encapsulant on the top side of the substrate, wherein the encapsulant contacts a side of the electronic device and a side of the component. Other examples and related methods are also disclosed herein.

A substrate processing method is a method of processing a substrate on which a metal-containing liquid for a film below a resist is applied, wherein prior to a heating process of performing a heat treatment on the substrate applied with the metal-containing liquid, the substrate processing method includes: a deprotection promoting process of promoting deprotection of functional groups in a material for the film included in the substrate on which the metal-containing liquid has been applied; a solvent removing process of removing a solvent included in the metal-containing liquid on the substrate; and a moisture absorbing process of bringing a surface of the substrate into contact with moisture.

An integrated circuit that includes micro-etched channels on a bottom surface is provided. The integrated circuit includes a lead frame having electrically conductive contact terminal pads and a die centrally disposed in the lead frame. Wire bonds provide an electrical connection from the die to the electrically conductive contact terminal pads. A mold compound encapsulates the die and the wire bonds, where a bottom surface of the mold compound is flush with a bottom surface of the contact terminal pads. A channel is defined in the bottom surface of the mold compound around a periphery of the contact terminal pads.

A microelectronics package assembly and process of making same are disclosed. The flange has an upper surface and a first coating disposed on the upper surface of the flange. The insulator has a bottom surface for mounting onto the flange and an upper surface opposite the bottom surface. A second coating is disposed on the bottom surface of the insulator and a third coating disposed on the upper surface of the insulator. The first coating, the second coating, and the third coating each have a thickness of less than or equal to 1 micron. At least one of the first coating, the second coating, and the third coating is applied via at least one of physical vapor deposition, atomic deposition, or chemical deposition.

An electronic package includes an electronic component including terminals, a plurality of leads, at least some of the leads being electrically coupled to the terminals within the electronic package, and a mold compound covering the electronic component and partially covering the leads. Each of the leads include an exposed bottom face coplanar with a bottom surface of the mold compound and an exposed end face coplanar with one of a plurality of side surfaces of the mold compound. For at least some of the leads, the exposed end face includes a narrow portion forming a concave recess, the narrow portion being between top and bottom edges of the exposed end face.

An extremely thin copper foil is provided that enables formation of highly fine different wiring patterns with a line/space (L/S) of 10 μm or less/10 μm or less on two sides of the copper foil and is thus usable as an inexpensive and readily processable substitution for silicon and glass interposers. The extremely thin copper foil includes, in sequence, a first extremely thin copper layer, an etching stopper layer, and the second extremely thin copper layer. Two sides of the extremely thin copper foil each have an arithmetic average roughness Ra of 20 nm or less.

A pre-molded leadframe includes a laminar structure having empty spaces therein and a first thickness with a die pad having opposed first and second die pad surfaces. Insulating pre-mold material is molded onto the laminar structure. The pre-mold material penetrates the empty spaces and provides a laminar pre-molded substrate having the first thickness with the first die pad surface left exposed. The die pad has a second thickness that is less than the first thickness. One or more pillar formations are provided protruding from the second die pad surface to a height equal to a difference between the first and second thicknesses. With the laminar structure clamped between surfaces of a mold, the first die pad surface and pillar formations abut against the mold surfaces. The die pad is thus effectively clamped between the clamping surfaces countering undesired flashing of the pre-mold material over the first die pad surface.

A lead frame includes: a frame body; a plurality of leads individually projecting from the frame body; and a recess formed across one surfaces of the leads adjacent to each other with the frame body therebetween, the recess including a first recess, and a second recess partially overlapping the first recess in a bottom surface thereof and having a smaller depth than the first recess.

A package substrate based on a molding process may include an encapsulation layer, a support frame located in the encapsulation layer, a base, a device located on an upper surface of the base, a copper boss located on a lower surface of the base, a conductive copper pillar layer penetrating the encapsulation layer in the height direction, and a first circuit layer and a second circuit layer over and under the encapsulation layer. The second circuit layer includes a second conductive circuit and a heat dissipation circuit, the first circuit layer and the second conductive circuit are connected conductively through the conductive copper pillar layer, the heat dissipation circuit is connected to one side of the device through the copper boss and the base, and the first circuit layer is connected to the other side of the device.