A semiconductor device, including a first metal strip extending in a first direction on a first plane; a second metal strip extending in the first direction on a second plane over the first metal strip; a third metal strip immediate adjacent to the second metal strip and extending in the first direction on the second plane; and a fourth metal strip immediate adjacent to the third metal strip and extending in the first direction on the second plane; wherein the first metal strip and the second metal strip are directed to a first voltage source; wherein a distance between the second metal strip and the third metal strip is greater than a distance between the third metal strip and the fourth metal strip.

Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.

In a described example, a method includes: forming cavities in a die mount surface of a package substrate, the cavities extending into the die mount surface of the package substrate at locations corresponding to post connects on a semiconductor die to be flip-chip mounted to the package substrate; placing flux in the cavities; placing solder balls on the flux; and performing a thermal reflow process and melting the solder balls to form solder pads in the cavities on the package substrate.

Semiconductor packages and methods for manufacturing are disclosed. In one example, a method for manufacturing a semiconductor package includes providing an electrically conductive chip carrier including a mounting surface and a protrusion extending out of the mounting surface. At least one semiconductor chip is arranged on the mounting surface. The method further includes encapsulating the protrusion and the at least one semiconductor chip in an encapsulation material, wherein surfaces of the protrusion and the at least one semiconductor chip facing away from the mounting surface remain uncovered by the encapsulation material. An electrical redistribution layer is formed over the surfaces of the protrusion and the at least one semiconductor chip facing away from the mounting surface. The electrical redistribution layer provides an electrical connection between the protrusion and the at least one semiconductor chip.

A method of forming a packaged semiconductor device according to some embodiments includes providing a leadframe blank including a first package blank, a second package blank and a tie bar between the first package blank and the second package blank, forming a recessed cavity in the tie bar, and separating the first and second package blanks by sawing through the leadframe blank along the tie bar.

This disclosure relates to a leadless packaged semiconductor device including a top and a bottom opposing major surfaces and sidewalls extending between the top and bottom surfaces, the leadless packaged semiconductor device further includes a lead frame structure including an array of two or more lead frame sub-structures each having a semiconductor die arranged thereon, and terminals and a track extended across the bottom surface of the semiconductor device. The track provides a region for interconnecting the semiconductor die and terminals, and the track is filled by an insulating material to isolate the lead frame sub-structures.

The present application provides a method for fabricating a semiconductor device including providing a semiconductor substrate, forming a first stress-relieving structure including a first conductive frame above the semiconductor substrate and a plurality of first insulating pillars within the first conductive frame, forming a second stress-relieving structure comprising a plurality of second conductive pillars above the first stress-relieving structure and a second insulating frame, the plurality of second conductive pillars are disposed within the second conductive frame, wherein the plurality of second conductive pillars is disposed correspondingly above the plurality of first insulating pillars, and the second insulating frame is disposed correspondingly above the first conductive frame; and forming a conductive structure including a supporting portion above the second stress-relieving structure, a conductive portion adjacent to the supporting portion, and a plurality of spacers attached to two sides of the conductive portion.

A substrate structure and a semiconductor package structure including the same are provided. The substrate structure includes a circuit layer and a dielectric structure. The circuit layer has a bottom surface and a top surface opposite to the bottom surface. The dielectric structure around the circuit layer. The dielectric structure covers a first part of the bottom surface of the circuit layer, and exposes a second part of the bottom surface and the top surface of the circuit layer. The dielectric structure exposes the top surface of the circuit layer. In addition, a method of manufacturing a semiconductor package structure is also provided.

The present disclosure is directed to a leadframe package having a side solder ball contact and methods of manufacturing the same. A plurality of solder balls are coupled to recesses in a leadframe before encapsulation and singulation. After singulation, a portion of each solder ball is exposed on sidewalls of the package. This ensures that the sidewalls of the leads are solder wettable, which allows for the formation of stronger joints when the package is coupled to a substrate. This increased adhesion reduces resistance at the joints and also mitigates the effects of expansion of the components in the package such that delamination is less likely to occur. As a result, packages with a side solder ball contact have increased life cycle expectancies.

According to a first aspect of the present invention there is provided a quad-flat-no-leads (QFN) packaged semiconductor device having a QFN bottom surface and QFN side faces, wherein the QFN side faces each comprise an upper portion and a recessed lower portion, the QFN packaged semiconductor device comprising: a die pad within or on the QFN bottom surface; a plurality of I/O terminals spaced apart from the die pad and around a periphery of the bottom surface, each having a bottom face extending from an inner end to a peripheral end, an exposed side face on a QFN side face and extending above the recessed lower portion of the QFN side face; wherein the QFN bottom surface includes at least one trench therein, parallel to a one of the QFN side faces and exposing at least a part of a side face of the inner end of the I/O terminals. The trench may provide for additional surface area, and provide a stronger solder joint when the QFN packaged semiconductor device is soldered to a substrate or circuit board.