A semiconductor package includes a substrate, a semiconductor die, dendrite, and a mold material. The substrate includes a die pad. The die pad includes roughening features. The semiconductor die is attached to the die pad such that the roughening features are adjacent to the semiconductor die. The dendrite is on the roughening features adjacent to the semiconductor die. The mold material encapsulates the semiconductor die, the dendrite, and at least a portion of the substrate.

A semiconductor package includes a lead frame, a chip, and a molding encapsulation. The lead frame comprises a die paddle, a first plurality of leads, additional one or more leads, a second plurality of leads, a first tie bar, a second tie bar, a third tie bar, and a fourth tie bar. A respective end surface of each lead of the first plurality of leads, the additional one or more leads, and the second plurality of leads is plated with a metal. A respective end surface of the first tie bar, the second tie bar, the third tie bar, and the fourth tie bar is not plated with the metal. A method for fabricating a semiconductor package includes the steps of providing a lead frame array, mounting a chip, forming a molding encapsulation, applying a trimming process, applying a plating process, and applying a singulation process.

The present disclosure describes a method of forming an epitaxial layer on a substrate in a chamber. The method includes cleaning the chamber with a first etching gas and depositing the epitaxial layer on the substrate. Deposition of the epitaxial layer includes epitaxially growing a first portion of the epitaxial layer with a precursor, cleaning the substrate and the chamber with a flush of a second etching gas different from the first etching gas, and epitaxially growing a second portion of the epitaxial layer with the precursor. The first portion and the second portion have the same composition. The method furthers includes etching a portion of the epitaxial layer with a third etching gas having a flow rate higher than that of the second etching gas.

A waterjet nozzle is provided for deflashing a leadless package device. The waterjet nozzle has a central core having a conically shaped passage between a nozzle inlet, lying in a first plane, and a nozzle outlet, lying in a second plane. The nozzle includes a groove, in the waterjet nozzle, above a third plane defining an end of the waterjet nozzle, along a first line in the third plane. A tube connects the nozzle outlet to the groove. The nozzle includes a flange, lying below the third plane along a second line, in the third plane, intersecting the first line. The waterjet nozzle may be used to deflash a leadframe package by inserting the flange from a waterjet nozzle into a singulation cut on a lead frame; and injecting a waterjet through the conically-shaped passage from the nozzle inlet through the nozzle outlet.

A leadless integrated circuit (IC) package includes a spaced apart plurality of lead terminals on at least two sides of the leadless IC package, and an IC die including a substrate having at least a semiconductor surface including circuitry coupled to bond pads with the bond pads having bonding features thereon. The bonding features are flip chip bonded to the plurality of lead terminals. Mold compound is above the IC die and between adjacent lead terminals. The lead terminals and the substrate both extend out to have exposed surfaces at edges of the leadless IC package, and the lead terminals also provide a back side bondable contact.

A semiconductor device package includes a copper lead frame, a copper oxide compound layer and an encapsulant. The copper oxide compound layer is in contact with a surface of the copper lead frame. The copper oxide compound layer includes a copper(II) oxide, and a thickness of the copper oxide compound layer is in a range from about 50 nanometers to about 100 nanometers. The encapsulant is in contact with a surface of the copper oxide compound layer.

A semiconductor package includes a substrate, a semiconductor die, dendrite, and a mold material. The substrate includes a die pad. The die pad includes roughening features. The semiconductor die is attached to the die pad such that the roughening features are adjacent to the semiconductor die. The dendrite is on the roughening features adjacent to the semiconductor die. The mold material encapsulates the semiconductor die, the dendrite, and at least a portion of the substrate.

A method includes removing an oxide layer from select areas of a surface of a metal structure of a lead frame to create openings that extend through the oxide layer to expose portions of the surface of the metal structure. The method further includes attaching a semiconductor die to the lead frame, performing an electrical connection process that electrically couples an exposed portion of the surface of the metal structure to a conductive feature of the semiconductor die, enclosing the semiconductor die in a package structure, and separating the electronic device from the lead frame. In one example, the openings are created by a laser ablation process. In another example, the openings are created by a chemical etch process using a mask. In another example, the openings are created by a plasma process.

Plasma applications are disclosed that operate with argon and other molecular gases at atmospheric pressure, and at low temperatures, and with high concentrations of reactive species. The plasma apparatus and the enclosure that contains the plasma apparatus and the substrate are substantially free of particles, so that the substrate does not become contaminated with particles during processing. The plasma is developed through capacitive discharge without streamers or micro-arcs. The techniques can be employed to remove organic materials from a substrate, thereby cleaning the substrate; to activate the surfaces of materials, thereby enhancing bonding between the material and a second material; to etch thin films of materials from a substrate; and to deposit thin films and coatings onto a substrate; all of which processes are carried out without contaminating the surface of the substrate with substantial numbers of particles.

After a die bonding step, a wire bonding step is performed to electrically connect the plurality of pad electrodes and the plurality of leads of the semiconductor chip via a plurality of copper wires. A plating layer is formed on a surface of the lead, and a copper wire is connected to the plating layer in the wire bonding step. The plating layer is a silver plating layer. After the die bonding step, an oxygen plasma treatment is performed on the lead frame and the semiconductor chip before the wire bonding step, and then the surface of the plating layer is reduced.