A method of manufacturing a power amplifier package embedded with an input-output circuit including a dielectric circuit board, a heat sink and lead frames, the method comprising: the step of preparing the dielectric circuit board including the steps of forming a power amplifier hole in which a power amplifier chip is to be disposed on a dielectric substrate, printing an input matching network metal pattern on a left side of the power amplifier hole, and printing an output matching network metal pattern on a right side of the power amplifier hole, and sintering the input matching network metal pattern and the output matching network metal pattern printed on the dielectric substrate; the step of preparing the lead frames by etching alloy 42 and plating nickel; and the step of attaching the heat sink on a bottom surface of the dielectric circuit board.

An apparatus is provided which comprises: a first die having at least one bond pad; a first flexible layer comprising an anisotropic conductive material, wherein the first flexible layer is adjacent to the at least one bond pad such that it makes an electrical contact with the at least one bond pad; and a second flexible layer comprising a conductive metal, wherein the second flexible layer is adjacent to the first flexible layer.

A lead frame used to assemble a semiconductor device, such as a smart card, has a first major surface including exposed leads and a second major surface including a die receiving area and one or more connection pads surrounding the die receiving area. The connection pads enable electrical connection of an Integrated Circuit (IC) die to the exposed leads. A molding tape sized and shaped like the lead frame is adhered to and covers the second major surface of the lead frame. The molding tape has a die receiving area cut-out that exposes the die receiving area and the connection pads on the second major surface of the lead frame and forms a cavity for receiving an encapsulant. The cut-out has an elevated sidewall for retaining the encapsulant within the cavity.

A method of manufacturing a semiconductor device is provided. The method includes attaching a first end of a first bond wire to a first conductive lead and a second end of the first bond wire to a first bond pad of a first semiconductor die. A conductive lead extender is affixed to the first conductive lead by way of a conductive adhesive, the lead extender overlapping the first end of the first bond wire. A first end of a second bond wire is attached to the lead extender, the first end of the second bond wire conductively connected to the first end of the first bond wire.

Leadframes for semiconductor devices are manufactured by providing a laminar substrate of laser direct structuring material, the laminar substrate comprising first and second opposed surfaces, applying laser beam processing to the substrate to provide a first pattern of electrically-conductive formations at the first surface, a second pattern of electrically-conductive formations at the second surface and electrically-conductive vias through the substrate between the first surface and the second surface. Electrically-conductive material is formed, for instance via electrolytic or electroless growth of electrically-conductive material such a copper onto the first and second pattern of electrically-conductive formations as well as onto the electrically-conductive vias provided by applying laser beam processing to the substrate. The electrically-conductive vias are coupled to one or both of the electrically-conductive formations in the first pattern of electrically-conductive formations and the second pattern of electrically-conductive formations.

A method of forming a semiconductor device is provided. The method includes placing a semiconductor die and a leadframe on a carrier substrate. The semiconductor die includes a plurality of bond pads and the leadframe includes a plurality of leads. A first lead of the plurality of leads has a proximal end affixed to a first bond pad of the plurality of bond pads and a distal end placed on the carrier substrate. At least a portion of the semiconductor die and the leadframe is encapsulated with an encapsulant. The carrier substrate is separated from a first major side of the encapsulated semiconductor die and leadframe exposing a distal end portion of the first lead. A package substrate is applied on the first major side.

The present invention relates to a process of a surface-mounting three-dimensional package structure electrically connected by a pre-packaged metal, comprising: taking a metal sheet; punching or etching the metal sheet; packaging a conductive metal-pillar frame; performing windowing and slotting; taking a substrate on which a chip is surface-mounted; fitting the conductive metal-pillar frame; performing packaging and grinding; surface-mounting a passive device; performing plastic packaging and ball-mounting; and performing cutting. The process of the present invention can improve the integration level and the reliability.

Provided are a method for fabricating a semiconductor package and a semiconductor package using the same, which can simplify a fabricating process of the semiconductor package by forming a lead frame on which a semiconductor die can be mounted without a separate grinding process, and can improve product reliability by preventing warpage from occurring during a grinding process. In one embodiment, the method for fabricating a semiconductor package includes forming a frame on a carrier, forming a first pattern layer on the frame, first encapsulating the frame and the first pattern layer using a first encapsulant, forming conductive vias electrically connected to the first pattern layer while passing through the first encapsulant, forming a second pattern layer electrically connected to the conductive vias on the first encapsulant, forming a first solder mask formed on the first encapsulant and exposing a portion of the second pattern layer to the outside, removing the frame by an etching process and etching a portion of the first pattern layer, and attaching a semiconductor die to the first pattern layer.

A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed. A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads. A semiconductor die is electrically connected to the surface finish layer and an encapsulant covers the semiconductor die and another side of the first resin layer. The surface finish layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded lead frame structure.

A busbar assembly according to the present invention includes a first busbar formed by a conductive metal flat plate; a second busbar formed by a conductive metal flat plate, the second busbar disposed in the same plane as the first busbar with a gap being provided between opposing side surfaces of the first and second busbars; and an insulating resin layer filled in the gap so as to mechanically connect the opposing side surfaces of the first and second busbars. Preferably, the opposing side surface of at least one of the first and second busbars is an inclined surface that is closer to the opposing side surface of the other of the first and second busbars from one side toward the other side in the thickness direction.