A package that includes an integrated device, a substrate coupled to the integrated device, and an encapsulation layer coupled to the substrate. The encapsulation layer encapsulates the integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects located in the at least one dielectric layer, wherein at least one of the interconnects has a rectangular side cross-section having at least one corner with a corner radius less than a corner radius threshold.

A bi-facial solar cell includes a silicon substrate, a first doped region formed on a front surface of the silicon substrate, an oxide layer formed on a back surface of the silicon substrate, a second doped region formed on the oxide layer and formed of a polycrystalline silicon layer, a first passivation layer formed on the first doped region, a first anti-reflection layer formed on the first passivation layer, a plurality of first finger electrodes connected to the first doped region through a first opening in the first passivation layer and the first anti-reflection layer, a second passivation layer formed on the second doped region, a second anti-reflection layer formed on the second passivation layer, and a plurality of second finger electrodes connected to the second doped region through a second opening in the second passivation layer and the second anti-reflection layer.

The disclosure is and includes at least an apparatus, system and method for a ramped electrical interconnection for use in semiconductor fabrications. The apparatus, system and method includes at least a first semiconductor substrate having thereon a first electrical circuit comprising first electrical components; a second semiconductor substrate at least partially covering the first electrical circuit, and having thereon a second electrical circuit comprising second electrical components; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component.

A method for manufacturing a semiconductor device includes forming a lead frame assembly in which a first side wall portion and a second side wall portion, both made of a resin, are joined to each other in a state of having a metal lead frame sandwiched therebetween; applying a sintering metal paste to a disposition region of the lead frame assembly and disposing the lead frame assembly on the sintering metal paste; and sintering the sintering metal paste between a metal base of the semiconductor device and the lead frame assembly to join the base and the lead frame assembly to each other.

Provided are a stretchable electronic device and a method for manufacturing the same. The stretchable electronic device includes lines having lower pads, a chip provided on the lower pads and having first upper pads, which are wider than the lower pads, and an adhesive layer provided outside the lower pads or between the lower pads and bonded to the first upper pads.

An object of the present invention is to provide a method for accurately forming an antenna substrate as well as an antenna substrate with wiring line and electrode by a coating method. One aspect of the present invention provides a method for producing an antenna substrate with wiring line and electrode including the steps of: (1) forming a coating film using a photosensitive paste containing a conductive material and a photosensitive organic component on an insulating substrate; (2-A) processing the coating film into a pattern corresponding to an antenna by photolithography; (2-B) processing the coating film into a pattern corresponding to a wiring line; (2-C) processing the coating film into a pattern corresponding to an electrode; (3-A) curing the pattern corresponding to an antenna into an antenna; (3-B) curing the pattern corresponding to a wiring line into a wiring line; and (3-C) curing the pattern corresponding to an electrode into an electrode.

Techniques for fabricating a semiconductor package comprising inductor features and a magnetic film are described. For one technique, fabricating a package includes: forming inductor features comprising a pad and a conductive line on a first build-up layer; forming a raised pad structure on the first build-up layer by fabricating a pillar structure on the pad, wherein a size of the pillar structure is approximately equal or equal to a corresponding size of the pad such that the pillar structure and the pad are aligned or minimally misaligned relative to each other; encapsulating the inductor features and the raised pad structure in a magnetic film; planarizing the magnetic film until top surfaces of the raised pad structure and magnetic film are co-planar; depositing an additional layer on the top surfaces; and forming a via on the raised pad structure by removing portions of the additional layer above the raised pad structure.

The purpose of the present invention is to provide an electronic component in which a copper electrode and an inorganic substrate exhibit strong adhesion to each other. A method for producing an electronic component according to the present invention comprises: an application step wherein a paste is applied onto an inorganic substrate, which paste contains copper particles, copper oxide particles and/or nickel oxide particles, and inorganic oxide particles having a softening point: a sintering step wherein a sintered body which contains at least copper is formed by means of heating in an inert gas atmosphere at a temperature that is less than the softening point of the inorganic oxide particles but not less than the sintering temperature of the copper particles; and a softening step wherein hearing is carried out in an inert gas atmosphere at a temperature that is not less than the softening point of the inorganic oxide particles.

A method for manufacturing an electronic device includes providing a substrate with a first major surface having a microchannel, wherein the microchannel has a first end and a second end; dispensing a conductive liquid in the microchannel to cause the conductive liquid to move, primarily by capillary pressure, in a first direction toward the first end of the microchannel and in a second direction toward the second end of the microchannel; and solidifying the conductive liquid to form an electrically conductive trace electrically connecting a first electronic device at the first end of the microchannel to a second electronic device at the second end of the microchannel.

A component carrier with a first component carrier structure including a first stack which has at least one first electrically conductive layer structure and at least one first electrically insulating layer structure is disclosed. The at least one first electrically conductive layer structure has a first contact element which extends up to a first contact surface of the first stack. An electrically conductive connection medium is directly connected to the first contact element at the first contact surface by filling at least one recess of the first contact element. The at least one recess having a larger dimensioned cavity delimited by a smaller dimensioned surface profile.