A method for producing a copper multi-level metallization on a ceramic substrate consisting of AlN or Al.sub.2O.sub.3. High power regions with metallization having a high current-carrying capacity and low power regions with metallic coatings having a low current-carrying capacity are created on one and the same ceramic substrate. The metallization is printed multiple times in the high power range.

A method for packaging a circuit component, comprising: forming a first protruding pad on a first copper substrate and a through-hole in the first protruding pad; forming a second protruding pad on a second copper substrate and placing a circuit dice of the circuit component on the second protruding pad having a conductive paste coated thereon wherein a first electrode of the dice facing the second protruding pad; stacking the first copper substrate onto the second copper substrate with the first protruding pad having a conductive paste coated thereon aligned and pressing onto the circuit dice placed on the second protruding pad wherein a second electrode of the dice facing the first protruding pad; inserting a copper rod tightly into the through-hole until contacting with a conductive paste coated on the second substrate; heat-treating the stacked structure for the circuit dice and the copper rod to form secured electrical connection with the first and second copper substrates respectively and further forming a hermetic seal in the space between the first and second copper substrates; and using the hermetic seal as a rigid processing structure, etching the exposed surface of the first and second copper substrates to remove the entire thickness of copper other than in the area of the first and second protruding pads and in the area other than where the copper rod connects to the second copper substrate, thereby forming the device terminals of the circuit component package.

A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface. The semiconductor package may also include a first semiconductor die having a first bond pad on a first die surface, where the first semiconductor die is bonded to the first surface of the CSDS via the first bond pad, and a second semiconductor die having a second bond pad on a second die surface, where the second semiconductor die is bonded to the second surface of the CSDS via the second bond pad. The semiconductor package may further include a metal post electrically coupled to the first surface of the CSDS, and a first encapsulant material encapsulating side surfaces and a surface opposite the first die surface of the first semiconductor die, the metal post, and a portion of the first surface of the CSDS.

A chip package, in some embodiments, comprises: a die flag; one or more die supports; and a die mounted on the die flag and on said one or more die supports, at least one surface of said die having an area larger than an area of at least one surface of the die flag.

A method of forming a solder connection includes forming a solder mask on a thermal pad of a printed circuit board. The solder mask leaves unmasked portions of the thermal pad and forming the solder mask includes forming a plurality of mask stripes extending from edges of each unmasked portion towards a center of the unmasked portion. The method includes depositing solder paste on the unmasked portions of the thermal pad and placing an exposed thermal pad of an integrated circuit package on the solder paste deposited on the thermal pad of the printed circuit board. The method includes forming a solder connection by heating the solder paste between the unmasked portions of the thermal pad on the printed circuit board and the exposed thermal pad of the integrated circuit package.

Generally discussed herein are systems and apparatuses that include a dense interconnect bridge and techniques for making the same. According to an example a technique can include creating a multidie substrate, printing an interconnect bridge on the multidie substrate, electrically coupling a first die to a second die by coupling the first and second dies through the interconnect bridge.

A method of manufacturing component carriers includes carrying out a test for each of multiple sections of a component-carrier structure, inserting at least one functional component in each of further sections of a further component-carrier structure to be connected with the component-carrier structure so that each further section assigned to a respective section having successfully passed the test is provided with at least one functional component, and inserting at least one functionally inactive dummy component in each of the further sections assigned to a respective section having failed the test.

A semiconductor package includes a substrate having a first surface, a second surface opposite the first surface, and interconnect patterns disposed therein, a semiconductor device mounted on the first surface of the substrate, a layer of sealing resin sealing the semiconductor device, a plurality of external connection electrodes formed on the second surface of the substrate, an electromagnetic wave shield film for blocking electromagnetic waves, which is formed on an upper surface of the layer of sealing resin and side surfaces of the layer of sealing resin and the substrate, and a ground interconnect formed on the substrate and electrically connected to the electromagnetic wave shield film.

An article includes a solid circuit die on a first major surface of a substrate, wherein the solid circuit die includes an arrangement of contact pads, and wherein at least a portion of the contact pads in the arrangement of contact pads are at least partially exposed on the first major surface of the substrate to provide an arrangement of exposed contact pads; a guide layer including an arrangement of microchannels, wherein the guide layer contacts the first major surface of the substrate such that at least some microchannels in the arrangement of microchannels overlie the at least some exposed contact pads in the arrangement of exposed contact pads; and a conductive particle-containing liquid in at least some of the microchannels. Other articles and methods of manufacturing the articles are described.

A package that includes an integrated device, a substrate coupled to the integrated device, and an encapsulation layer coupled to the substrate. The encapsulation layer encapsulates the integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects located in the at least one dielectric layer, wherein at least one of the interconnects has a rectangular side cross-section having at least one corner with a corner radius less than a corner radius threshold.