In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate which has a plurality of element regions and of which an element surface is covered by insulating film, the substrate is divided into element chips by exposing the substrate to a first plasma, element chips having first surface, second surface, and side surface are held spaced from each other on carrier, insulating film is in a state of being exposed, recessed portions are formed by retreating insulating film by exposing element chips to second plasma for ashing, and then recessed portions are covered by protection films by third plasma for formation of the protection film, thereby suppressing creep-up of the conductive material to side surface in the mounting step.

A solar cell includes a silicon substrate, an emitter area formed on a front surface of the silicon substrate, a tunneling oxide layer formed on a back surface of the silicon substrate, a back surface field area formed on the tunneling oxide layer and formed of a polycrystalline silicon layer, a back passivation film formed on the back surface field area and having an opening, and a back electrode connected to the back surface field area via the opening.

A package structure is provided. The package structure includes a semiconductor die structure over a substrate and bonding structures between the semiconductor die and the substrate. The package structure also includes multiple solder elements over the substrate. The solder elements together surround the semiconductor die structure, and each of the solder elements is longer than a side of the semiconductor die structure. The package structure further includes an underfill material surrounding the bonding structures. The underfill material is substantially confined within a region surrounded by the solder elements. The underfill material is in direct contact with at least one of the solder elements.

Temperature sensor packages and methods of fabrication are described. The temperature sensor packages in accordance with embodiments may be rigid or flexible. In some embodiments the temperature sensor packages are configured for touch sensing, and include an electrically conductive sensor pattern such as a thermocouple or resistance temperature detector (RTD) pattern. In some embodiments, the temperature sensor packages are configured for non-contact sensing an include an embedded transducer.

A master tool is provided with an ink pattern on a major surface thereof. The ink pattern is formed by a screen printing process. A stamp-making material is applied to the major surface of the master tool to form a stamp having a stamping pattern being negative to the ink pattern of the master tool. The stamping pattern is inked with an ink composition and contacted with a metalized surface to form a printed pattern on a metalized surface of a substrate according to the stamping pattern. Using the printed pattern as an etching mask, the metalized surface is etched to form electrically conductive traces on the substrate.

A method of manufacturing electronics using a nanoparticle ink printing method includes: synthesizing a phase change material (PCM) ink composition using hot injection to develop nanoparticles of the PCM; suspending the nanoparticles with a solvent; and printing a reconfigurable component using the PCM ink composition in additive manufacturing. Electronics includes: a substrate layer; an insulator layer printed on top of the substrate layer; a heater layer printed on top of the insulator layer; a barrier layer printed on top of one or more of the insulator layer and the heater layer; a phase change material (PCM) printed on top of the barrier layer; a connectivity layer printed on top of the PCM; and a passivation layer printed on top of one or more of the PCM and the connectivity layer.

Disclosed is an integrated circuit arrangement including a two sided circuit board, having a first surface and a second surface. A plurality of electrical conductors is incorporated as part of the two sided circuit board. An array of through holes extend through the first surface and the second surface, arranged in a pattern and are configured to provide a common electrical connection area, wherein the common electrical connection area is associated with a portion of a particular one of the plurality of electrical conductors.

BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold solder paste material applied to the mold, for example with a solder paste printing process. The depth and/or diameter of the cavities may be predetermined as a function of spatial position within the mold working surface area. Mold cavity dimensions may be specified corresponding to package position to account for one or more pre-existing or expected spatial variations in the package, such as a package-level warpage measurement. Any number of different ball heights may be provided. The molds may be employed in a standardize process that need not be modified with each change in the mold.

In one aspect, a method of packaging a semiconductor module includes providing a semiconductor module having a first surface, a second surface opposite the first surface and edge sides extending between the first surface and the second surface. A packaging assembly is formed at least partly by a 3D printing process. The packaging assembly includes the semiconductor module and a protective covering that extends over the first surface.

Methods and compositions are described for controlling bond line thickness of a joint formed during sintering. Spacer particles of a predetermined particle type and size are added in a predetermined concentration to a sintering paste to form a sintering paste mixture prior to sintering to achieve a targeted bond line thickness during sintering. The sintering paste mixture can be sintered under pressure and pressure-less process conditions. Under pressured sintering, the amount of pressure applied during sintering may be adjusted depending on the composition and concentration of the spacer particles to adjust bond line thickness.