A method of making a package is disclosed. The method may include forming bond pads on a first surface of a substrate, forming leads in the substrate by etching recesses in a second surface of the substrate, the second surface being opposite the first surface, and plating at least a portion of a top surface of the leads with a layer of finish plating. The method may also include thermosonically bonding the leads to a die by thermosonically bonding the finish plating to the die and encapsulating the die and the leads in an encapsulant.

A compliant pin fin heat sink includes a flexible base plate having a thickness of from about 0.2 mm to about 0.5 mm. A plurality of pins extends from the flexible base plate and is formed integral with the flexible base plate by forging. A flexible top plate is connected to and spaced from the flexible base plate. The plurality of pins is disposed between the flexible base plate and the flexible top plate.

A method for packaging a circuit component, comprising: forming a first protruding pad on a first copper substrate and a through-hole in the first protruding pad; forming a second protruding pad on a second copper substrate and placing a circuit dice of the circuit component on the second protruding pad having a conductive paste coated thereon wherein a first electrode of the dice facing the second protruding pad; stacking the first copper substrate onto the second copper substrate with the first protruding pad having a conductive paste coated thereon aligned and pressing onto the circuit dice placed on the second protruding pad wherein a second electrode of the dice facing the first protruding pad; inserting a copper rod tightly into the through-hole until contacting with a conductive paste coated on the second substrate; heat-treating the stacked structure for the circuit dice and the copper rod to form secured electrical connection with the first and second copper substrates respectively and further forming a hermetic seal in the space between the first and second copper substrates; and using the hermetic seal as a rigid processing structure, etching the exposed surface of the first and second copper substrates to remove the entire thickness of copper other than in the area of the first and second protruding pads and in the area other than where the copper rod connects to the second copper substrate, thereby forming the device terminals of the circuit component package.

A power semiconductor module includes: a substrate including first, second, and third metal patterns separated from each other, a semiconductor element located on the substrate, a lead frame located on the substrate and including first, second, third, and fourth bodies; a first terminal connected to the first body, a second terminal connected to the second body, and a third common terminal that connects the third body and the fourth body, wherein a length of the third common terminal is longer than that of the first and second terminals.

A fingerprint identification module includes a substrate, a fingerprint sensor die, a covering adhesive layer, a cover plate and a mold compound layer. The fingerprint sensor die is attached on the substrate for sensing a fingerprint image. The covering adhesive layer is formed on a top surface of the fingerprint sensor die. The cover plate is attached on the covering adhesive layer. The mold compound layer is formed over the substrate. The fingerprint sensor die, the covering adhesive layer and the cover plate over the substrate are molded together through the mold compound layer, and the cover plate is exposed. The fingerprint identification module has small thickness and enhanced sensing accuracy.

A method is provided to fabricate a high-power module. A non-touching needle is used to paste a slurry on a heat-dissipation substrate. The slurry comprises nano-silver particles and micron silver particles. The ratio of the two silver particles is 9:1˜1:1. The slurry is pasted on the substrate to be heated up to a temperature kept holding. An integrated chip (IC) is put above the substrate to form a combined piece. A hot presser processes thermocompression to the combined piece to form a thermal-interface-material (TIM) layer with the IC and the substrate. After heat treatment, the TIM contains more than 99 percent of pure silver with only a small amount of organic matter. No volatile organic compounds would be generated after a long term of use. No intermetallic compounds would be generated while the stability under high temperature is obtained. Consequently, embrittlement owing to procedure temperature is dismissed.

A manufacturing method of a chip package structure includes following steps. A substrate including a first metal layer, a second metal layer, and an insulation layer located between the first and the second metal layers is provided. A first groove is formed in the first metal layer to form a chip pad and bonding pads. The bonding pads are respectively located in recesses of the chip pad. A second groove is formed in the second metal layer to form a heat-dissipation block and terminal pads. The terminal pads are respectively located in recesses of the heat-dissipation block. Conductive vias are formed to connect the corresponding terminal pads and electrically connect the bonding pads with the terminal pads. A chip is disposed on the chip pad and electrically connected to the bonding pads. An encapsulant covering the chip is formed.

A circuit substrate includes: a base material; and a capacitor layer. The capacitor layer includes a first metal layer that is provided on the base material, a dielectric layer that is provided on the first metal layer, and a second metal layer that is provided on the dielectric layer. The first metal layer includes a first electrode region which is provided on the base material and is exposed from the dielectric layer and to which a first terminal of a capacitor element for supplying current to a circuit part through the capacitor layer is connected. The second metal layer includes a second electrode region in which the second metal layer is exposed and to which a second terminal of the capacitor element is connected.

Apparatus and techniques herein related battery plates. For example, a first battery plate can include a conductive silicon wafer. A first mechanical support can be located on a first side of the conductive silicon wafer. A first active material can be adhered to the first mechanical support and the first side of the conductive silicon wafer, the first active material having a first polarity. In an example, the battery plate can be a bipolar plate, such as having a second mechanical support located on a second side of the conductive silicon wafer opposite the first side, and a second active material adhered to the second mechanical support and the second side of the conductive silicon wafer, the second material having an opposite second polarity.

An integrated circuit (IC) package includes a substrate and an IC die carried by the substrate. An encapsulated body is over the IC die. At least one grounding wire is within the encapsulated body and has a proximal end coupled to the substrate and a distal end exposed on an outer surface of the encapsulated body. An electrically conductive shield layer is on the outer surface of the encapsulated body and in contact with the exposed distal end of the at least one grounding wire.