Disclosed is a fan-out antenna packaging method. A front surface of a semiconductor chip is jointed to a top surface of a separating layer; side surfaces and a bottom surface of the semiconductor chip are merged into a packaging layer; the packaging layer is separated from the separating layer to expose the front surface of the semiconductor chip; a rewiring layer is electrically connected to the semiconductor chip; a first antenna structure and a second antenna are stacked on a top surface of the rewiring layer, the antenna structures is electrically connected to the rewiring layer; a through hole runs through the packaging layer and exposes a metal wiring layer in the rewiring layer; and a metal bump electrically connected to the metal wiring layer is formed by using the through hole.

Methods for processing a metal substrate for use in a power electronics device are provided. In one example, the method includes placing a metal substrate on a support associated with a laser system. The method includes performing a pulsed laser treatment process on at least a portion of the surface of the metal substrate. The pulsed laser treatment process exposes the at least a portion of the surface of the metal substrate to a plurality of laser pulses to modify a surface roughness of the at least a portion of the surface of the metal substrate. After performing the pulsed laser treatment process, the method includes creating a metallized interface for coupling an electrical component to the metal substrate at the at least a portion of the surface of the metal substrate.

An electronic device module includes a substrate, a first device and a second device mounted on the substrate, and a shielding frame mounted on the substrate to accommodate the first device. The shielding frame includes a heat dissipating portion stacked on the first device, and posts extended from an edge of the heat dissipating portion and spaced apart from each other. A spacing distance between the posts is smaller than a wavelength of an electromagnetic wave introduced into the first device or output from the first device.

In one example, a semiconductor device comprises an electronic component comprising a component face side, a component base side, a component lateral side connecting the component face side to the component base side, and a component port adjacent to the component face side, wherein the component port comprises a component port face. A clip structure comprises a first clip pad, a second clip pad, a first clip leg connecting the first clip pad to the second clip pad, and a first clip face. An encapsulant covers portions of the electronic component and the clip structure. The encapsulant comprises an encapsulant face, the first clip pad is coupled to the electronic component, and the component port face and the first clip face are exposed from the encapsulant face. Other examples and related methods are also disclosed herein.

An integrated circuit includes an oxide layer over a substrate; a layer of semiconductor material over the oxide layer and which includes a P-well, an N-well, and a channel of a transistor; and a thermal substrate contact extending through the layer of semiconductor material and the oxide layer, and against a top surface of the substrate. A thermal substrate contact increases the ability to remove heat produced from the integrated circuit transistors out of the integrated circuit. A thermal substrate contact which traverses the oxide layer over a substrate provides a secondary path for heat out of an integrated circuit (or, alternatively, out of a substrate through the integrated circuit) to cool the integrated circuit.

The object is to provide a technology of controlling warpage of a metal base plate occurring in temperature change from high temperature to room temperature by causing warpage in the metal base plate in temperature change from room temperature to high temperature. A dissimilar metal layer is formed on a surface of a metal base plate. An insulation substrate is joined to a surface of the dissimilar metal layer with a joining material being provided between the insulation substrate and the surface of the dissimilar metal layer, and includes metal plates disposed on both surfaces. α1>α3>α2 is satisfied, where α1 represents a linear expansion coefficient of the metal base plate, α2 represents a linear expansion coefficient of the dissimilar metal layer, and α3 represents a linear expansion coefficient of the metal plates.

A chip packaging method includes: providing plural chip units; providing a base material, and placing the chip units on the base material; providing an adhesive layer to adhere a metal foil to the chip unit, wherein the metal foil is a part of the base material or additional to the base material; and cutting the chip units on the base material to form plural separated chip package units, wherein each of the chip package units includes a cut metal foil part.

A joined body production method includes subjecting a first electronic component and a second electronic component to thermocompression bonding via a hot-melt adhesive sheet. The hot-melt adhesive sheet includes a binder and solder particles. The binder includes a crystalline polyamide resin having a carboxyl group. A melting point of the solder particles is 30° C. to 0° C. lower than a temperature of the thermocompression bonding. When melt viscosities of the hot-melt adhesive sheet are measured under a condition of a heating rate of 5° C./min., the hot-melt adhesive sheet has a ratio of a melt viscosity at 40° C. lower than the temperature of the thermocompression bonding to a melt viscosity at 20° C. lower than the temperature of the thermocompression bonding of no less than 10.

An apparatus comprises conductive segments comprising an uneven topography comprising upper surfaces of the conductive segments protruding above an upper surface of underlying materials, a first passivation material substantially conformally overlying the conductive segments, and a second passivation material overlying the first passivation material. The second passivation material is relatively thicker than the first passivation material. The apparatus also comprises structural elements overlying the second passivation material. The second passivation material has a thickness sufficient to provide a substantially flat surface above the uneven topography of the underlying conductive segments at least in regions supporting the structural elements. Microelectronic devices, memory devices, and related methods are also disclosed.

A package is disclosed. The package can include a package substrate that has an opening, such as a through hole, extending from a top side to a bottom side opposite the top side of the package substrate. The package can also include a component at least partially disposed in the through hole. The component can be an electrical component. The component can be exposed at a bottom surface of the package. The package can include a bonding material that mechanically couples the component and the package substrate.