A package structure and the method thereof are provided. At least one die is molded in a molding compound. A ground plate is located on a backside surface of the die, a first surface of the ground plate is exposed from the molding compound and a second surface of the ground plate is covered by the molding compound. The first surface of the ground plate is levelled and coplanar with a third surface of the molding compound. A connecting film is located between the backside surface of the die and the second surface of the ground plate. The die, the molding compound and the ground plate are in contact with the connecting film. Through interlayer vias (TIVs) are molded in the molding compound, and at least one of the TIVs is located on and physically contacts the second surface of the ground plate.

A semiconductor and a method of fabricating the semiconductor having multiple, interconnected die including: providing a semiconductor substrate having a plurality of disparate die formed within the semiconductor substrate, and a plurality of scribe lines formed between pairs of adjacent die of the plurality of disparate die; and fabricating, by a lithography system, a plurality of inter-die connections that extend between adjacent pair of die of the plurality of die.

A semiconductor memory device according to an embodiment includes a memory cell array that includes memory cells and a plurality of first conducting layers. The memory cells are arrayed in a three-dimensional manner. The first conducting layers are connected to the memory cells and are arrayed in a laminating direction. Stepped wiring portion includes a plurality of second conducting layers. The plurality of second conducting layers connect the first conducting layers and external circuits. At least one of the plurality of second conducting layers includes a contact formation area on a top surface thereof in the stepped wiring portion positioned on the first side portion side. Other ones of the plurality of second conducting layers includes a contact formation area on a top surface thereof in the stepped wiring portion positioned on the second side portion side.

A manufacturing method of a POP structure including at least the following steps is provided. A first package structure is formed and a second package structure is formed on the first package structure. The first package structure includes a circuit carrier and a die disposed on the circuit carrier. Forming the first package structure includes providing a conductive interposer on the circuit carrier, encapsulating the conductive interposer by an encapsulant and removing a portion of the encapsulant and the plate of the conductive interposer. The conductive interposer includes a plate, a plurality of conductive pillars and a conductive protrusion respectively extending from the plate to the circuit carrier and the die. The conductive protrusion disposed on the die, and the conductive pillars are electrically connected to the circuit carrier. The second package structure is electrically connected to the first package structure through the conductive interposer.

A method includes aligning a wire with a package body having a contact pad and moving the wire through the package body to form electrical contact with the contact pad.

An electronic device structure having a shielding structure includes a substrate with an electronic component electrically connected to the substrate. The shielding structure includes conductive spaced-apart pillar structures that have proximate ends connected to the substrate and distal ends spaced apart from the substrate, and that are laterally spaced apart from the first electronic component. In one embodiment, the conductive pillar structures are conductive wires attached at one end to the substrate with an opposing end extending away from the substrate so that the conductive wires are provided generally perpendicular to the substrate. A package body encapsulates the electronic component and the conductive spaced-apart pillar structures. In one embodiment, the shielding structure further includes a shielding layer disposed adjacent the package body, which is electrically connected to the conductive spaced-apart pillar structures. In one embodiment, the electrical connection is made through the package. In another embodiment, the electrical connection is made through the substrate.

A component such as an interposer or microelectronic element can be fabricated with a set of vertically extending interconnects of wire bond structure. Such method may include forming a structure having wire bonds extending in an axial direction within one of more openings in an element and each wire bond spaced at least partially apart from a wall of the opening within which it extends, the element consisting essentially of a material having a coefficient of thermal expansion (CTE) of less than 10 parts per million per degree Celsius (ppm/ C.). First contacts can then be provided at a first surface of the component and second contacts provided at a second surface of the component facing in a direction opposite from the first surface, the first contacts electrically coupled with the second contacts through the wire bonds.

A semiconductor device includes a shielding wire formed across a semiconductor die and an auxiliary wire supporting the shielding wire, thereby reducing the size of a package while shielding the electromagnetic interference generated from the semiconductor die. In one embodiment, the semiconductor device includes a substrate having at least one circuit device mounted thereon, a semiconductor die spaced apart from the circuit device and mounted on the substrate, a shielding wire spaced apart from the semiconductor die and formed across the semiconductor die, and an auxiliary wire supporting the shielding wire under the shielding wire and formed to be perpendicular to the shielding wire. In another embodiment, a bump structure is used to support the shielding wire. In a further embodiment, an auxiliary wire includes a bump structure portion and wire portion and both the bump structure portion and the wire portion are used to support the shielding wire.

A module includes a circuit package having multiple electronic components on a substrate, a molded compound disposed over the substrate and the electronic components, and an external shield disposed on at least one outer surface of the circuit package. The external shield is segmented into multiple external shield partitions that are grounded, respectively. Adjacent external shield partitions of the multiple external shield partitions are separated by a corresponding gap located between adjacent electronic components of the multiple electronic components. The external shield is configured to protect the circuit package from external electromagnetic radiation and environmental stress. Each corresponding gap separating the adjacent external shield partitions is configured to provide internal shielding of at least one of the electronic components, between which the corresponding gap is located, from internal electromagnetic radiation generated by the other of the adjacent electronic components.

Provided is a semiconductor device with improved reliability that achieves the reduction in size. A semiconductor wafer is provided that has a first insulating member with an opening that exposes from which an upper surface of an electrode pad. Subsequently, after forming a second insulating member over a main surface of the semiconductor wafer, another opening is formed to expose the upper surface of the electrode pad. Then, a probe needle is brought into contact with the electrode pad, to write data in a memory circuit at the main surface of the semiconductor wafer. After covering the upper surface of the electrode pad with a conductive cover film, a relocation wiring is formed. In the Y direction, the width of the relocation wiring positioned directly above the electrode pad is equal to or smaller than the width of the opening formed in the first insulating member.