The present disclosure provides an electronic package. The electronic package includes a substrate, an electronic component, a plurality of conductive elements, a metal sheet and a molding layer. The electronic component is disposed on the substrate and electrically connected to the substrate. The conductive elements are disposed on the substrate and electrically connected with the grounding circuit on the substrate. The metal sheet is disposed above the electronic component and is in electrical contact with the conductive elements. The molding layer is formed between the substrate and the metal sheet to enclose the electronic component and the conductive elements. The present disclosure further provides a method of manufacturing the above electronic package.

A semiconductor device has a substrate and a plurality of bond wires is disposed in a pattern across on the substrate. The pattern of bond wires can be a plurality of rows of bond wires. A plurality of electrical components is disposed over the substrate as an SIP module. An encapsulant is deposited over the substrate, electrical components, and bond wire. An opening is formed in the encapsulant extending to the bond wire. The opening can be a trench extending across the bond wires disposed on the substrate, or a plurality of openings individually exposing each of a plurality of bond wires. A conductive material is disposed in the opening. A shielding layer is formed over the encapsulant and in contact with the conductive material. The shielding layer, conductive material, and bond wires reduce the effects of EMI, RFI, and other inter-device interference.

A manufacturing method for a chip packaging structure, comprising: arranging a metal heat dissipation layer on a substrate comprising at least one flange on its side surface; forming a sealing pin located on an upper surface of the flange, so that the metal heat dissipation layer, the flange and the sealing pin form a cavity for accommodating an encapsulant; attaching a chip structure on an upper surface of the metal heat dissipation layer using an adhesive layer; forming the encapsulant encapsulating an upper surface of the substrate, the metal heat dissipation layer and the chip structure, the sealing pin extends to a periphery of the upper surface of the encapsulant; performing a mechanical or chemical treatment, to make electrode connecting structures on an upper layer of the chip structure exposed outside the first encapsulant; arranging a pin layer for electrically coupling to and covering the electrode connection structures.

A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.

A semiconductor package is described. The semiconductor packager includes a chip stack mounted on a package substrate, a first wire disposed on the package substrate, and a molding layer surrounding the chip stack and the first wire. The first wire has an acute angle.

An antenna package includes a conductive layer, an interconnection structure and an antenna. The interconnection structure is disposed on the conductive layer. The interconnection structure includes a conductive via and a first package body. The conductive via has a first surface facing the conductive layer, a second surface opposite to the first surface and a lateral surface extending from the first surface to the second surface. The first package body covers the lateral surface of the conductive via and exposes the first surface and the second surface of the conductive via. The first package body is spaced apart from the conductive layer. The antenna is electrically connected to the second surface of the conductive via.

A method of producing electronic components including at least one circuit having coupled therewith electrical connections including metallic wire bondable surfaces encased in a packaging, the method including bonding stud bumps, in particular copper stud bumps, at determined areas of said wire bondable surfaces.

A package structure and the method thereof are provided. The package structure includes a conductive plate, a semiconductor die, a molding compound, and antenna elements. The conductive plate has a first surface, a second surface and a sidewall connecting the first surface and the second surface. The semiconductor die is located on the second surface of the conductive plate. The molding compound laterally encapsulates the semiconductor die and covers the sidewall and a portion of the second surface exposed by the semiconductor die, wherein the first surface of the conductive plate is coplanar with a surface of the molding compound. The antenna elements are located over the first surface of the conductive plate.

A method of fabricating (a distributed write driving arrangement for a semiconductor memory device) includes: forming bit cells and a local write driver in a first device layer; forming a local write bit (LWB) line and a local write bit_bar (LWB_bar) line in a first metallization layer; connecting each of the bit cells correspondingly between the LWB and LWB_bar lines; connecting the local write driver to the LWB line and the LWB_bar line; forming a global write bit (GWB) line and a global write bit_bar (GWBL_bar) line in a second metallization layer; connecting the GWB line to the LWB line; connecting the GWB line and the GWBL_bar line to the corresponding LWB line and LWB_bar line; forming a global write driver in a second device layer; and connecting the global write driver to the GWB line and the GWBL_bar line.

A semiconductor device package includes a carrier, an electronic component and a connector. The electronic component is disposed on the carrier. The connector is disposed on the carrier and electrically connected to the electronic component. A S11 parameter of the connector is less than −20 dB.