A semiconductor package structure includes a plurality of first dies spaced from each other, a molding layer between the first dies, a second die over the plurality of first dies and the molding layer, and an adhesive layer between the plurality of first dies and the second die, and between the molding layer and the second die. A first interface between the adhesive layer and the molding layer and a second interface between the adhesive layer and the plurality of first dies are at different levels.

A lead frame includes a lead frame body processed in a predetermined shape, and including a notched part provided at an end of the lead frame body, the notched part being used as a starting point of tape-removing, a resin leakproof tape stuck on a back surface of the lead frame body, and a region of a periphery of the notched part in the back surface of the lead frame body, the region being reduced in a strength of bonding between the resin leakproof tape and the lead frame body is reduced relative to other region.

A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.

Disclosed are semiconductor devices and methods of fabricating the same. The method comprises providing a carrier substrate that includes a conductive layer, placing a semiconductor die on the carrier substrate, forming an insulating layer to cover the semiconductor die on the carrier substrate, forming a via hole to penetrate the insulating layer at a side of the semiconductor die and to expose the conductive layer of the carrier substrate, performing a plating process in which the conductive layer of the carrier substrate is used as a seed to form a via filling the via hole, forming a first redistribution layer on a first surface of the semiconductor die and the insulating layer, removing the carrier substrate, and forming a second redistribution layer on a second surface of the semiconductor die and the insulating layer, the first surface and the second surface being located opposite each other.

A package component, a semiconductor package and a manufacturing method thereof are provided. The package component for electrically coupling a semiconductor die includes a functional circuit structure and a seal ring structure embedded in an insulating layer. The semiconductor die disposed on the package component is electrically coupled to the functional circuit structure. The seal ring structure is electrically isolated from the functional circuit structure, the seal ring structure includes a stack of alternating interconnect layers and via patterns, the via pattern at each level of the stack includes first features spaced apart from one another and arranged at neighboring corners of the insulating layer, and the first features are offset lengthwise relative to each other to overlap therewith, and the first features are spaced apart widthwise relative to each other.

A laminate including a glass plate and a coating layer, wherein the coating layer includes one or more components selected from the group consisting of silicon nitride, titanium oxide, alumina, niobium oxide, zirconia, indium tin oxide, silicon oxide, magnesium fluoride, and calcium fluoride, wherein a ratio (dc/dg) of a thickness dc of the coating layer to a thickness dg of the glass plate is in a range of 0.05×10.sup.−3 to 1.2×10.sup.−3, and wherein a radius of curvature r1 of the laminate with negating of self-weight deflection is 10 m to 150 m.

Package-on-Package (PoP) structures and methods of forming the same are disclosed. In some embodiments, a method of forming a PoP structure may include: plating at least one through-assembly via (TAV) over a peripheral region of a conductive seed layer; forming a dam member over a central region of the conductive seed layer; and placing a die over the central region of the conductive seed layer. The dam member may be laterally separated from the die and disposed between the die and the at least one TAV. The method may further include encapsulating the die, the dam member, and the at least one TAV in a polymer material.

Apparatuses and methods are described. This apparatus includes a bridge die having first contacts on a die surface being in a molding layer of a reconstituted wafer. The reconstituted wafer has a wafer surface including a layer surface of the molding layer and the die surface. A redistribution layer on the wafer surface includes electrically conductive and dielectric layers to provide conductive routing and conductors. The conductors extend away from the die surface and are respectively coupled to the first contacts at bottom ends thereof. At least second and third IC dies respectively having second contacts on corresponding die surfaces thereof are interconnected to the bridge die and the redistribution layer. A first portion of the second contacts are interconnected to top ends of the conductors opposite the bottom ends thereof in part for alignment of the at least second and third IC dies to the bridge die.

A method of placing a protective member on a workpiece includes a sheet producing step of heating a plate-shaped thermoplastic resin to soften or melt the same while gripping and pulling outer edges of the thermoplastic resin in at least four directions to produce a sheet-like protective member, and after the sheet producing step, an integrating step of heating and bringing the sheet-like protective member into intimate contact with the workpiece to integrate the workpiece and the protective member with each other.

The invention relates to a method for moulding and surface processing electronic components wherein a grid of electronic components is attached on a carrier; subsequently foil is placed against the side of the electronic components opposite to the carrier and are the electronic components partially encapsulated. After moulding the foil is removed from the electronic components and a free side of the components is surface processed. The invention also relates to a partial encapsulated electronic component as produced with such a method.