A release film satisfies formulas (I) and (II) when S1 (%) represents the maximum dimensional change rate between 30° C. and 150° C. when the temperature is raised from 30° C. to 200° C. at a rate of 10° C./min, T1 (° C.) represents the temperature at which S1 is obtained, and S0 (%) represents the dimensional change rate at 40° C. The surfaces may have a surface free energy Sa (mN/mm) at 25° C., surface free energy Sb (mN/mm) after having been subjected to a heat treatment at 180° C. for 3 minutes, and surface free energy Sc (mN/mm) after having been stretched by 50% at 180° C. that satisfy formulas (III) and (IV).
0≤S1≤1.5  Formula (I):
0≤|S1−S0|/(T1−40)≤0.050  Formula (II):
0≤|Sa−Sb|≤15  Formula (III):
0≤|Sa−Sc|≤15  Formula (IV):

Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor structures terminate in the molding layer and anchor the molding layer to the package substrate.

A manufacturing method of a package structure including the following steps is provided. A carrier is provided. An anti-warpage structure is formed on the carrier. And a redistribution layer is formed on the carrier. In the normal direction of the carrier, a warpage trend of the anti-warpage structure is opposite to a warpage trend of the redistribution layer.

A MEMS pressure sensor packaged with a molding compound. The MEMS pressure sensor features a lead frame, a MEMS semiconductor die, a second semiconductor die, multiple pluralities of bonding wires, and a molding compound. The MEMS semiconductor die has an internal chamber, a sensing component, and apertures. The MEMS semiconductor die and the apertures are exposed to an ambient atmosphere. A method is desired to form a MEMS pressure sensor package that reduces defects caused by mold flashing and die cracking. Fabrication of the MEMS pressure sensor package comprises placing a lead frame on a lead frame tape; placing a MEMS semiconductor die adjacent to the lead frame and on the lead frame tape with the apertures facing the tape and being sealed thereby; attaching a second semiconductor die to the MEMS semiconductor die; attaching pluralities of bonding wires to form electrical connections between the MEMS semiconductor die, the second semiconductor die, and the lead frame; and forming a molding compound.

A package structure includes at least one semiconductor die, an insulating encapsulant, an isolation layer and a redistribution layer. The at least one first semiconductor die has a semiconductor substrate and a conductive post disposed on the semiconductor substrate. The insulating encapsulant is partially encapsulating the first semiconductor die, wherein the conductive post has a first portion surrounded by the insulating encapsulant and a second portion that protrudes out from the insulating encapsulant. The isolation layer is disposed on the insulating encapsulant and surrounding the second portion of the conductive post. The redistribution layer is disposed on the first semiconductor die and the isolation layer, wherein the redistribution layer is electrically connected to the conductive post of the first semiconductor die.

A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.

Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a platform has an upper surface and a lower surface opposite the upper surface and has a ground plane. A microelectronic device is coupled to the upper surface of the platform. Wire bond wires are coupled to the ground plane with a pitch. The wire bond wires extend away from the upper surface of the platform with upper ends of the wire bond wires extending above an upper surface of the microelectronic device. The wire bond wires are spaced apart from one another to provide a fence-like perimeter to provide an interference shielding cage. A conductive layer is coupled to at least a subset of the upper ends of the wire bond wires for electrical conductivity to provide a conductive shielding layer to cover the interference shielding cage.

A wafer- or panel-level encapsulated package comprises a glass substrate comprising a glass cladding layer (105) fused to a glass core layer (110), the glass substrate comprising a cavity (425), wherein the glass cladding layer has a higher etch rate in an etchant than the glass core layer. The wafer- or panel-level encapsulated package further comprises a microelectronic component (700) disposed in the cavity, and an encapsulant (702) sealed to the glass substrate such that the microelectronic component is encapsulated within the cavity. Methods for forming the wafer- or panel-level encapsulated package, including etching a cavity into a glass substrate, depositing a microelectronic component into the cavity, and sealing an encapsulant to the glass substrate such that the microelectronic component is encapsulated within the cavity are also provided.

A semiconductor package and a manufacturing method thereof are provided. A package substrate of a device includes a functional circuit structure in a central region of the package substrate and a seal ring structure in a peripheral region of the package substrate and electrically isolated from the functional circuit structure. The seal ring structure includes a via pattern including outer discrete features arranged in an outer loop and inner discrete features arranged in an inner loop between the outer loop and the functional circuit structure. In a top view, ends of adjacent two of the inner discrete features are spaced apart from each other by a non-zero distance, and one of the outer discrete features overlaps the non-zero distance.

A system for thinning a substrate includes a chuck and a first liquid supply unit. The chuck includes a base portion and a frame portion disposed on the base portion, where the substrate is configured to be placed on a carrying surface of the chuck. The first liquid supply unit extends along sidewalls the frame portion and the base portion, an outlet of the first liquid supply unit is disposed next to the carrying surface of the chuck, the first liquid supply unit delivers a first liquid from a bottom of the chuck to the outlet, and the first liquid discharges from the outlet to cover a sidewall of the substrate.