A cover for an integrated circuit package includes a central plate and a peripheral frame surrounding the central plate. The peripheral frame is vertically spaced from and parallel to the central plate. The peripheral frame includes through openings formed therein. The cover can be used to package a semiconductor chip that is mounted to a substrate.

An electronic device structure includes a substrate having a substrate first major surface, an opposing substrate second major surface, and a first conductive pattern adjacent to the substrate first major surface. A first electronic component is coupled to the substate and includes a first component first side and a first device structure adjacent to the first component first side. A second electronic component is adjacent to the substate second major surface and includes a second component first side and a second device structure adjacent to the second component first side. A third electronic component is coupled to the substrate. The first electronic component is generally orthogonal to the substrate and the first device structure is oriented in a first direction, and the second device structure is oriented in a second direction different than the first direction.

A flip-chip bonding structure includes a chip and a circuit board, the chip is bonded to the circuit board by bumps. The circuit board includes a light-transmissive substrate, a first circuit group, a second circuit group, a boundary circuit and an identifying member. The boundary circuit is located between the first and second circuit groups and projects a boundary circuit shadow on light-transmissive substrate. The boundary circuit shadow can be recognized according to the identifying member and is provided to identify the boundary between the first and second circuit groups or identify the position of leads with the smallest pitch.

Electronic packages and methods of formation are described in which an interposer is solderlessly connected with a package substrate. The interposer may be stacked on the package substrate and joined with a conductive film, and may be formed on the package substrate during a reconstitution sequence.

The present disclosure includes a semiconductor package including a redistribution layer (RDL) having a first surface in contact with input/output (I/O) contacts and a second surface opposite to the first surface. The semiconductor package also includes a staircase interconnect structure formed on the second surface of the RDL and electrically connected with the RDL. The staircase interconnect structure includes staircase layers including a first staircase layer and a second staircase layer stacked on a top surface of the first staircase layer. The second staircase layer covers a portion of the top surface of the first staircase layer such that a remaining portion of the top surface of the first staircase layer is exposed. Integrated circuit (IC) chips are electrically connected to the RDL via the staircase interconnect structure. A first IC chip of the IC chips is electrically connected to the RDL through the remaining portion of the top surface of the first staircase layer.

Electronic packages and methods of formation are described in which an interposer is solderlessly connected with a package substrate. The interposer may be stacked on the package substrate and joined with a conductive film, and may be formed on the package substrate during a reconstitution sequence.

A chip component including a first electrode and a second electrode, a semiconductor device including a first land and a second land, and a printed wiring board are prepared. A first solder paste and a second solder paste are supplied to the printed wiring board. The chip component is placed on the printed wiring board so that the first electrode is in contact with the first solder paste and the second electrode is in contact with the second solder paste. The semiconductor device is placed on the printed wiring board so that the first land faces the first electrode and the second land faces the second electrode. The solder paste is heated and melted, the first land and the first electrode are bonded to each other, and the second land and the second electrode are bonded to each other.

A method for manufacturing a semiconductor device of an embodiment includes: dividing a semiconductor wafer including a plurality of chip areas each having a columnar electrode and dicing areas, along the dicing areas to form a plurality of semiconductor chips; sticking a first resin film on the plurality of semiconductor chips while filling parts of the first resin film in gaps each present between adjacent ones of the plurality of semiconductor chips; forming trenches narrower in width than the gaps in the first resin film filled in the gaps; and sequentially picking up the plurality of semiconductor chips each having the first resin film, and mounting the picked semiconductor chip on a substrate.

Embossed solder masks for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a package substrate includes the solder mask with non-planar features along a surface of the solder mask such that the area of the surface is increased. The non-planar features may correspond to concave recesses formed on the surface of the solder mask. Physical dimensions (e.g., widths, depths) and/or areal densities of the non-planar features of the embossed solder masks may vary based on local areas of the package substrate exclusive of conductive bumps. The non-planar features may be formed by pressing a mold having convex features against the surface of the solder mask. The solder mask may be heated while pressing the mold against the surface of the solder mask. In some embodiments, the mold includes regions lacking the convex features.

A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide methods for manufacturing a semiconductor device, and semiconductor devices produced thereby, that comprise forming an interposer including a reinforcement layer.