H01L21/67213

Multi-zone platen temperature control
11646213 · 2023-05-09 · ·

A system and method for etching workpieces in a uniform manner are disclosed. The system includes a semiconductor processing system that generates a ribbon ion beam, and a workpiece holder that scans the workpiece through the ribbon ion beam. The workpiece holder includes a plurality of independently controlled thermal zones so that the temperature of different regions of the workpiece may be separately controlled. In certain embodiments, etch rate uniformity may be a function of distance from the center of the workpiece, also referred to as radial non-uniformity. Further, when the workpiece is scanned, there may also be etch rate uniformity issues in the translated direction, referred to as linear non-uniformity. The present workpiece holder comprises a plurality of independently controlled thermal zones to compensate for both radial and linear etch rate non-uniformity.

Optical heat source with restricted wavelengths for process heating

A semiconductor manufacturing system or process, such as an ion implantation system, apparatus and method, including a component or step for heating a semiconductor workpiece are provided. An optical heat source emits light energy to heat the workpiece. The optical heat source is configured to provide minimal or reduced emission of non-visible wavelengths of light energy and emit light energy at a wavelength in a maximum energy light absorption range of the workpiece.

WAFER COOLING METHOD
20170352544 · 2017-12-07 ·

An ion implantation system has a first chamber and a process chamber with a heated chuck. A controller transfers the workpiece between the heated chuck and first chamber and selectively energizes the heated chuck first and second modes. In the first and second modes, the heated chuck is heated to a first and second temperature, respectively. The first temperature is predetermined. The second temperature is variable, whereby the controller determines the second temperature based on a thermal budget, an implant energy, and/or an initial temperature of the workpiece in the first chamber, and generally maintains the second temperature in the second mode. Transferring the workpiece from the heated chuck to the first chamber removes implant energy from the process chamber in the second mode. Heat may be further transferred from the heated chuck to a cooling platen by a transfer of the workpiece therebetween to sequentially cool the heated chuck.

Wafer Scanning Apparatus and Method for Focused Beam Processing
20230187168 · 2023-06-15 ·

A method of scanning a wafer includes placing the wafer over a substrate holder inside a processing chamber, where the wafer is placed at a first twist angle relative to a reference axis of a rotatable feedthrough of the processing chamber. The method further includes performing a first pass scan by exposing the wafer to an ion beam while driving two rotary drives disposed in a scanning chamber synchronously to generate a planar motion of the wafer from a rotational motion of the two rotary drives, where the wafer is oriented continuously at the first twist angle when performing the first pass scan.

Fluorinated compositions for ion source performance improvements in nitrogen ion implantation

Compositions, methods, and apparatus are described for carrying out nitrogen ion implantation, which avoid the incidence of severe glitching when the nitrogen ion implantation is followed by another ion implantation operation susceptible to glitching, e.g., implantation of arsenic and/or phosphorus ionic species. The nitrogen ion implantation operation is advantageously conducted with a nitrogen ion implantation composition introduced to or formed in the ion source chamber of the ion implantation system, wherein the nitrogen ion implantation composition includes nitrogen (N.sub.2) dopant gas and a glitching-suppressing gas including one or more selected from the group consisting of NF.sub.3, N.sub.2F.sub.4, F.sub.2, SiF4, WF.sub.6, PF.sub.3, PF.sub.5, AsF.sub.3, AsF.sub.5, CF.sub.4 and other fluorinated hydrocarbons of C.sub.xF.sub.y (x≧1, y≧1) general formula, SF.sub.6, HF, COF.sub.2, OF.sub.2, BF.sub.3, B.sub.2F.sub.4, GeF.sub.4, XeF.sub.2, O.sub.2, N.sub.2O, NO, NO.sub.2, N.sub.2O.sub.4, and O.sub.3, and optionally hydrogen-containing gas, e.g., hydrogen-containing gas including one or more selected from the group consisting of H.sub.2, NH.sub.3, N.sub.2H.sub.4, B.sub.2H.sub.6, AsH.sub.3, PH.sub.3, SiH.sub.4, Si.sub.2H.sub.6, H.sub.2S, H.sub.2Se, CH.sub.4 and other hydrocarbons of C.sub.xH.sub.y (x≧1, y≧1) general formula and GeH.sub.4.

Deposition of low-stress boron-containing layers

Examples of the present technology include semiconductor processing methods to form boron-containing materials on substrates. Exemplary processing methods may include delivering a deposition precursor that includes a boron-containing precursor to a processing region of a semiconductor processing chamber. A plasma may be formed from the deposition precursor within the processing region of the semiconductor processing chamber. The methods may further include depositing a boron-containing material on a substrate disposed within the processing region of the semiconductor processing chamber, where the substrate is characterized by a temperature of less than or about 50° C. The as-deposited boron-containing material may be characterized by a surface roughness of less than or about 2 nm, and a stress level of less-than or about −500 MPa. In some embodiments, a layer of the boron-containing material may function as a hardmask.

ION IMPLANTATION METHOD AND DEVICE

An ion implantation system comprising: a sample platform; an ion gun; an electrostatic linear accelerator; a direct current (DC) final energy magnet (FEM); and a processor. The processor is programmed to control: a wafer acceptance test instrument, a DC recipe calculator, a DC real energy calculator, and a tool energy shift verifier. The wafer acceptance test instrument is configured to apply a wafer acceptance test (WAT) recipe to a test sample on the sample platform. The DC recipe calculator is configured to calculate a recipe for the DC FEM. The DC real energy calculator is configured to calculate a real energy of the DC FEM. The tool energy shift verifier is configured to verify a tool energy shift of the DC FEM. The ion implantation system is configured to tune the DC FEM based on the verified tool energy shift, and obtain a peak magnetic field of the DC FEM.

INTEGRATED METROLOGY AND PROCESS TOOL TO ENABLE LOCAL STRESS/OVERLAY CORRECTION

Embodiments of the disclosure provide an integrated system for performing a measurement process and a lithographic overlay error correction process on a semiconductor substrate in a single processing system. In one embodiment, a processing system includes at least a load lock chamber, a transfer chamber coupled to the load lock chamber, an ion implantation processing chamber coupled to or in the transfer chamber, and a metrology tool coupled to the transfer chamber, wherein the metrology tool is adapted to obtain stress profile or an overlay error on a substrate disposed in the metrology tool.

Vacuum-integrated hardmask processes and apparatus

Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.

DEPOSITION OF LOW-STRESS BORON-CONTAINING LAYERS

Examples of the present technology include semiconductor processing methods to form boron-containing materials on substrates. Exemplary processing methods may include delivering a deposition precursor that includes a boron-containing precursor to a processing region of a semiconductor processing chamber. A plasma may be formed from the deposition precursor within the processing region of the semiconductor processing chamber. The methods may further include depositing a boron-containing material on a substrate disposed within the processing region of the semiconductor processing chamber, where the substrate is characterized by a temperature of less than or about 50° C. The as-deposited boron-containing material may be characterized by a surface roughness of less than or about 2 nm, and a stress level of less-than or about −500 MPa. In some embodiments, a layer of the boron-containing material may function as a hardmask.