A semiconductor structure includes a semiconductor substrate, a first isolation dam, a plurality of switching transistors and a second isolation dam. The semiconductor substrate includes a trench, an isolation region formed by a region where the trench is located, a plurality of active regions defined by the isolation region, and an electrical isolation layer, the electrical isolation layer being located on one side, away from an opening of the trench, of the trench; the first isolation dam fills the trench; the switching transistor is at least partially embedded in the active region of the semiconductor substrate; and the second isolation dam is at least partially located between the first isolation dam and the electrical isolation layer.

A method includes etching a semiconductor substrate to form a semiconductor strip and a recess, with a sidewall of the semiconductor strip being exposed to the recess, depositing a dielectric layer into the recess, and depositing a capping layer over the dielectric layer. The capping layer extends into the recess, and comprises silicon oxynitride. The method further includes filling remaining portions of the recess with dielectric materials, performing an anneal process to remove nitrogen from the capping layer, and recessing the dielectric materials, the capping layer, and the dielectric layer. The remaining portions of the dielectric materials, the capping layer, and the dielectric layer form an isolation region. A portion of the semiconductor strip protrudes higher than a top surface of the isolation region to form a semiconductor fin.

The present disclosure provides a method of manufacturing a semiconductor structure having an electrical contact. The method includes providing a semiconductor substrate; forming a dielectric structure over the semiconductor substrate, the dielectric structure having a trench; filling a polysilicon material in the trench of the dielectric structure; detecting the polysilicon material to determine a region of the polysilicon material having one or more defects formed therein; implanting the polysilicon material with a dopant material into the region; and annealing the polysilicon material to form a doped polysilicon contact.

Provided is a semiconductor device and a method of manufacturing the same and, more particularly, to a semiconductor device and a method of manufacturing the same seeking to simplify the manufacturing process and consequently improve efficiency and reliability by forming an isolation region (191) including a pre-DTI region (1911) and a DTI region (1913) in and/or on a substrate before depositing an interlayer dielectric, thereby avoiding a need for a separate etch stop layer.

A method includes forming a first trench and a second trench in a semiconductor substrate; forming a first mask over the semiconductor substrate, wherein the first mask is disposed in a first portion of the first trench and exposes the second trench and a second portion of the first trench; after forming the first mask, deepening the second trench and the second portion of the first trench; after deepening the second trench and the second portion of the first trench, removing the first mask; and after removing the first mask, filling a dielectric material in both the first and second trenches.

Methods of depositing a silicon oxide film are disclosed. One embodiment is a plasma enhanced atomic layer deposition (PEALD) process that includes supplying a vapor phase silicon precursor, such as a diaminosilane compound, to a substrate, and supplying oxygen plasma to the substrate. Another embodiment is a pulsed hybrid method between atomic layer deposition (ALD) and chemical vapor deposition (CVD). In the other embodiment, a vapor phase silicon precursor, such as a diaminosilane compound, is supplied to a substrate while ozone gas is continuously or discontinuously supplied to the substrate.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first isolation layer positioned in the substrate, a first treated flowable layer positioned between the first isolation layer and the substrate, a second isolation layer positioned in the substrate, and a second treated flowable layer positioned between the second isolation layer and the substrate. A width of the first isolation layer is greater than a width of the second isolation layer, and a depth of the first isolation layer is less than a depth of the second isolation layer.

A device includes a semiconductor substrate, a gate dielectric over the semiconductor substrate, and a gate electrode over the gate dielectric. The gate electrode has a first portion having a first thickness, and a second portion having a second thickness smaller than the first thickness. The device further includes a source/drain region on a side of the gate electrode with the source/drain region extending into the semiconductor substrate, and a device isolation region. The device isolation region has a part having a sidewall contacting a second sidewall of the source/drain region to form an interface. The interface is overlapped by a joining line of the firs portion and the second portion of the gate electrode.

Integrated circuits and methods of producing the same are provided herein. In accordance with an exemplary embodiment, an integrated circuit includes an SOI substrate with an active layer overlying a buried insulator layer that in turn overlies a handle layer. A source is defined within the active layer, and a gate well is also defined within the active layer. A first ultra shallow trench isolation extends into the active layer, where a first portion of the active layer is positioned between the first ultra shallow trench isolation and the buried insulator layer. The first ultra shallow trench isolation is positioned between the source and the gate well.

Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first deep trench isolation (DTI) structure in a substrate. A dielectric structure is over the substrate. An interconnect structure is in the dielectric structure. The interconnect structure includes a lower interconnect structure and an upper interconnect structure that are electrically coupled together. The upper interconnect structure includes a plurality of conductive plates. The plurality of conductive plates are vertically stacked and electrically coupled together. A back-side through substrate via (BTSV) is in the substrate and the dielectric structure. The BTSV extends from a conductive feature of the lower interconnect structure through the dielectric structure and the substrate. The conductive feature of the lower interconnect structure is at least partially laterally within a perimeter of the DTI structure. The BTSV is within the perimeter of the DTI structure.