A semiconductor single crystal structure may include a substrate; a defect trapping stack disposed on the substrate; and a semiconductor single crystal disposed on the defect trapping stack, and having a lattice mismatch with a crystal of the substrate, in which the defect trapping stack may include a first dielectric layer disposed on the substrate, and having at least one first opening, a second dielectric layer disposed on the first dielectric layer, and having at least one second opening, a third dielectric layer disposed on the second dielectric layer, and having at least one third opening, and a fourth dielectric layer disposed on the third dielectric layer, and having at least one fourth opening, and in which the semiconductor single crystal may extend to a region of the substrate defined in the at least one first opening through the at least one first to fourth opening.

Electronic device fins may be formed by epitaxially growing a first layer of material on a substrate surface at a bottom of a trench formed between sidewalls of shallow trench isolation (STI) regions. The trench height may be at least 1.5 times its width, and the first layer may fill less than the trench height. Then a second layer of material may be epitaxially grown on the first layer in the trench and over top surfaces of the STI regions. The second layer may have a second width extending over the trench and over portions of top surfaces of the STI regions. The second layer may then be patterned and etched to form a pair of electronic device fins over portions of the top surfaces of the STI regions, proximate to the trench. This process may avoid crystaline defects in the fins due to lattice mismatch in the layer interfaces.

A method for fabricating a semiconductor device includes forming an opening in a first epitaxial lateral overgrowth region to expose a surface of the semiconductor substrate within the opening. The method further includes forming an insulation region at the exposed surface of the semiconductor substrate within the opening and filling the opening with a second semiconductor material to form a second epitaxial lateral overgrowth region using a lateral epitaxial growth process.

A method of fabricating a semiconductor device can include the following steps: (i) providing an initial sub-assembly including a trench-defining layer having a top surface; (ii) refining the initial sub-assembly into a first trench-cut intermediate sub-assembly by removing material to form an upper tier of a trench extending downward from the top surface of the trench-defining layer, the upper tier of the trench including two lateral trench surfaces and a bottom trench surface; and (iii) refining the first trench-cut intermediate sub-assembly into a second trench-cut intermediate sub-assembly by selectively removing material in a downwards direction starting from the bottom surface of the trench to form a lower tier of the trench, with the selective removal of material leaving at least a first defect blocking member in the lower tier of the trench.

A method for forming fins on a semiconductor device includes etching trenches into a monocrystalline substrate to form first fins and forming a first dielectric layer at bottoms of the trenches. Second fins of a material having a different composition than the substrate are grown on sidewalls of the trenches. A second dielectric layer is formed over the second fins. The first fins are removed by etching. The second fins are processed to form fin field effect transistor devices.

A method for forming fins on a semiconductor device includes etching trenches into a monocrystalline substrate to form first fins and forming a first dielectric layer at bottoms of the trenches. Second fins of a material having a different composition than the substrate are grown on sidewalls of the trenches. A second dielectric layer is formed over the second fins. The first fins are removed by etching. The second fins are processed to form fin field effect transistor devices.

A method for forming fins on a semiconductor device includes etching trenches into a monocrystalline substrate to form first fins and forming a first dielectric layer at bottoms of the trenches. Second fins of a material having a different composition than the substrate are grown on sidewalls of the trenches. A second dielectric layer is formed over the second fins. The first fins are removed by etching. The second fins are processed to form fin field effect transistor devices.

A semiconductor structure including: trench-defining layer; an epitaxial layer; and a set of defect-blocking member(s). The trench-defining layer includes a trench surface which defines an elongated interior space called the trench. The epitaxial layer is grown epitaxially in the interior space of the trench. Each defect blocking member of the set of defect blocking members: (i) extends from a portion of trench surface into the interior space of the trench; and (ii) is located below a top surface of the epitaxial layer. The defect blocking member(s) are designed to arrest the propagation of generally-longitudinal defects in the epitaxial layer, as it is grown, where the generally-longitudinal defects are defects that propagate at least generally in the elongation direction of the trench.

A method for forming fins on a semiconductor device includes etching trenches into a monocrystalline substrate to form first fins and forming a first dielectric layer at bottoms of the trenches. Second fins of a material having a different composition than the substrate are grown on sidewalls of the trenches. A second dielectric layer is formed over the second fins. The first fins are removed by etching. The second fins are processed to form fin field effect transistor devices.

Electronic device fins may be formed by epitaxially growing a first layer of material on a substrate surface at a bottom of a trench formed between sidewalls of shallow trench isolation (STI) regions. The trench height may be at least 1.5 times its width, and the first layer may fill less than the trench height. Then a second layer of material may be epitaxially grown on the first layer in the trench and over top surfaces of the STI regions. The second layer may have a second width extending over the trench and over portions of top surfaces of the STI regions. The second layer may then be patterned and etched to form a pair of electronic device fins over portions of the top surfaces of the STI regions, proximate to the trench. This process may avoid crystalline defects in the fins due to lattice mismatch in the layer interfaces.