An integrated circuit device includes a portion of a support wafer (e.g., a handle wafer), silicon on insulator layer, a first active device, and a second active device. The first active device has a first semiconductor thickness in a dielectric layer (e.g., a buried oxide layer). The first active device is on the SOI layer. The second active device has a second semiconductor thickness in the same dielectric layer as the first active device. The supporting wafer supports the first active device and the second active device. The second active device is also on the SOI layer. The first and second thicknesses are different from one another.

Certain electronic applications, such as OLED display back panels, require small islands of high-quality semiconductor material distributed over a large area. This area can exceed the areas of crystalline semiconductor wafers that can be fabricated using the traditional boule-based techniques. This specification provides a method of fabricating a crystalline island of an island material, the method comprising depositing particles of the island material abutting a substrate, heating the substrate and the particles of the island material to melt and fuse the particles to form a molten globule, and cooling the substrate and the molten globule to crystallize the molten globule, thereby securing the crystalline island of the island material to the substrate. The method can also be used to fabricate arrays of crystalline islands, distributed over a large area, potentially exceeding the areas of crystalline semiconductor wafers that can be fabricated using boule-based techniques.

A method of forming a semiconductor device that includes providing regions of epitaxial oxide material on a substrate of a first lattice dimension, wherein regions of the epitaxial oxide material separate regions of epitaxial semiconductor material having a second lattice dimension are different than the first lattice dimension to provide regions of strained semiconductor. The regions of the strained semiconductor material are patterned to provide regions of strained fin structures. The epitaxial oxide that is present in the gate cut space obstructs relaxation of the strained fin structures. A gate structure is formed on a channel region of the strained fin structures separating source and drain regions of the fin structures.

Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

Methods are provided for fabricating semiconductor nanowires on a substrate. A nanowire template is formed on the substrate. The nanowire template defines an elongate tunnel which extends, laterally over the substrate, between an opening in the template and a seed surface. The seed surface is exposed to the tunnel and of an area up to about 210.sup.4 nm.sup.2. The semiconductor nanowire is selectively grown, via said opening, in the template from the seed surface. The area of the seed surface is preferably such that growth of the nanowire proceeds from a single nucleation point on the seed surface. There is also provided a method for fabricating a plurality of semiconductor nanowires on a substrate and a semiconductor nanowire and substrate structure.

A method of forming a semiconductor device that includes providing regions of epitaxial oxide material on a substrate of a first lattice dimension, wherein regions of the epitaxial oxide material separate regions of epitaxial semiconductor material having a second lattice dimension are different than the first lattice dimension to provide regions of strained semiconductor. The regions of the strained semiconductor material are patterned to provide regions of strained fin structures. The epitaxial oxide that is present in the gate cut space obstructs relaxation of the strained fin structures. A gate structure is formed on a channel region of the strained fin structures separating source and drain regions of the fin structures.

Methods are provided for fabricating semiconductor nanowires on a substrate. A nanowire template is formed on the substrate. The nanowire template defines an elongate tunnel which extends, laterally over the substrate, between an opening in the template and a seed surface. The seed surface is exposed to the tunnel and of an area up to about 210.sup.4 nm.sup.2. The semiconductor nanowire is selectively grown, via said opening, in the template from the seed surface. The area of the seed surface is preferably such that growth of the nanowire proceeds from a single nucleation point on the seed surface. There is also provided a method for fabricating a plurality of semiconductor nanowires on a substrate and a semiconductor nanowire and substrate structure.

A substrate for an integrated circuit includes a device wafer having a raw carrier concentration and an epitaxial layer disposed over the device wafer. The epitaxial layer has a first carrier concentration. The first carrier concentration is higher than the raw carrier concentration.

A method of forming a semiconductor device that includes providing regions of epitaxial oxide material on a substrate of a first lattice dimension, wherein regions of the epitaxial oxide material separate regions of epitaxial semiconductor material having a second lattice dimension are different than the first lattice dimension to provide regions of strained semiconductor. The regions of the strained semiconductor material are patterned to provide regions of strained fin structures. The epitaxial oxide that is present in the gate cut space obstructs relaxation of the strained fin structures. A gate structure is formed on a channel region of the strained fin structures separating source and drain regions of the fin structures.