A pattern forming method includes forming a first resist pattern on a substrate using imprint lithography. And forming a resist onto the substrate at least at positions corresponding to a second resist pattern and then curing the resist to form the second resist pattern on the substrate.

A method of manufacturing a structure that includes a substrate provided with a through hole, and a resin layer provided on a front surface of the substrate to close the through hole, includes, in order, preparing the substrate including the through hole and including a support substrate on a back surface of the substrate to close the through hole, bonding a dry film to a front surface of the substrate, the dry film including a support member and a resin layer on the support member, to close the through hole with the resin layer and turn the through hole into a closed space with the substrate, the support substrate, and the dry film, opening the through hole turned into the closed space from the support substrate side, and separating the support member from the dry film while retaining the resin layer on the front surface of the substrate.

A pattern forming method includes forming a first resist pattern on a substrate using imprint lithography. And forming a resist onto the substrate at least at positions corresponding to a second resist pattern and then curing the resist to form the second resist pattern on the substrate.

A semiconductor package according to an embodiment includes a semiconductor chip having a first surface in which a chip pad is formed, a first insulating layer arranged on the first surface of the semiconductor chip and including a first filler, a first conductive via electrically connected to the chip pad and formed to penetrate the first insulating layer, a redistribution pattern electrically connected to the first conductive via and buried in the first insulating layer, a second insulating layer contacting the redistribution pattern on the first insulating layer and including a second filler, a second conductive via electrically connected to the redistribution pattern and formed to penetrate the second insulating layer, an under bump material (UBM) electrically connected to the second conductive via and buried in the second insulating layer, and an external connection terminal electrically connected to the UBM.

Multi-patterning methods are provided for use in fabricating an array of metal lines comprising metal lines with different widths. For example, patterning methods implement spacer-is-dielectric (SID)-based self-aligned double patterning (SADP) methods for fabricating an array of metal lines comprising elongated metal lines with different widths, wherein an unblock mask is utilized as part of the process flow to overlap mandrel assigned and non-mandrel assigned features in a given SADP pattern to define regions to unblock a metal fill (remove dielectric material between wires) in a dielectric layer between defined metal lines of an a SADP pattern thus enabling the formation of wide metal lines within any region of a pattern of elongated metal lines formed with a minimum feature width.

An electronic device (100) includes a substrate (110) and an integrated circuit (120) provided on the substrate (110) having a surface facing away from the substrate (110). An insulating layer (150) extends over the substrate (110) and around the integrated circuit (120) to define an interface (154) between the insulating layer (150) and the integrated circuit (120). An electrically conductive via (130) is provided on the surface of the integrated circuit (120). An insulating material (140) extends over the via (130) and includes an opening (142) exposing a portion of the via (130). A repassivation member (162) extends over the insulating layer (150) and has a surface (164) aligned with the interface (154). An electrically conductive redistribution member (181) is electrically connected to the via (130) and extends over the repassivation member (162) into contact with the insulating layer (150).

A method and apparatus for forming a plurality of vias in panels for advanced packaging applications is disclosed, according to one embodiment. A redistribution layer is deposited on a substrate layer. The redistribution layer may be deposited using a spin coating process, a spray coating process, a drop coating process, or lamination. The redistribution layer is then micro-imprinted using a stamp inside a chamber. The redistribution layer and the stamp are then baked inside the chamber. The stamp is removed from the redistribution layer to form a plurality of vias in the redistribution layer. Excess residue built-up on the redistribution layer may be removed using a descumming process. A residual thickness layer disposed between the bottom of each of the plurality of vias and the top of the substrate layer may have thickness of less than about 1 m.

A carrier film according to an embodiment of the present invention comprises: a base film; and a first adhesive layer formed on a surface of the base film such that an element to be transferred is attached to the first adhesive layer, wherein the magnitude of force of adhesion between the element and the first adhesive layer is in proportion to the depth of press-fitting at which the element is press-fitted into the first adhesive layer.

A pattern forming method includes forming a first resist pattern on a substrate using imprint lithography. And forming a resist onto the substrate at least at positions corresponding to a second resist pattern and then curing the resist to form the second resist pattern on the substrate.

An imprint lithography stamp includes a stamp body having a patterned surface and formed from a fluorinated ethylene propylene copolymer. The imprint lithography stamp further includes a backing plate with a plurality of through-holes with portions of the stamp body extending into the through-holes to adhere the stamp body to the backing plate. The patterned surface of the stamp body has a plurality of protrusions extending from the stamp body, which are used to form high aspect ratio features at high processing temperatures. A mold design for forming the imprint lithography stamp and an injection molding process for forming the imprint lithography stamp are also provided.