Interconnect structures and processes generally include creating point defects in exposed surfaces of the dielectric layer to create a point defect region at a relatively shallow depth, wherein the point defect region is a fraction of the dielectric layer and is created with exposure to silicon, carbon, nitrogen, oxygen, or mixtures thereof such that the point defect region contains Si, C, N O, or mixtures containing at least one of the foregoing. A seed layer can be deposited and includes at least one alloying element that is effective to form an in situ self-aligned liner layer with the Si, C, N O, or mixtures containing at least one of the foregoing within the point defect region, which is formed at a depth of less than 10 nanometers. The in situ liner layer within the dielectric layer maximizes the volume fraction of the conductor of the interconnect structure.

The present disclosure provides a method of fabricating a semiconductor structure in accordance with some embodiments. The method includes receiving a substrate having an active region and an isolation region; forming gate stacks on the substrate and extending from the active region to the isolation region; forming an inner gate spacer and an outer gate spacer on sidewalls of the gate stacks; forming an interlevel dielectric (ILD) layer on the substrate; removing the outer gate spacer in the isolation region, resulting in an air gap between the inner gate spacer and the ILD layer; and performing an ion implantation process to the ILD layer, thereby expanding the ILD layer to cap the air gap.

An embodiment method includes: forming a gate stack over a channel region; growing a source/drain region adjacent the channel region; depositing a first ILD layer over the source/drain region and the gate stack; forming a source/drain contact through the first ILD layer to physically contact the source/drain region; forming a gate contact through the first ILD layer to physically contact the gate stack; performing an etching process to partially expose a first sidewall and a second sidewall, the first sidewall being at a first interface of the source/drain contact and the first ILD layer, the second sidewall being at a second interface of the gate contact and the first ILD layer; forming a first conductive feature physically contacting the first sidewall and a first top surface of the source/drain contact; and forming a second conductive feature physically contacting the second sidewall and a second top surface of the gate contact.

The present application discloses provides a method for fabricating a semiconductor device. The method includes providing a substrate, forming a sacrificial structure above the substrate, forming a supporting liner covering the sacrificial structure, forming an energy-removable layer covering the supporting liner, performing a planarization process until a top surface of the sacrificial structure is exposed, performing an etch process to remove the sacrificial structure and concurrently form a first opening in the energy-removable layer, forming covering liners on sidewalls of the first opening and on a top surface of the energy-removable layer, forming a first conductive feature in the first opening, and applying an energy source to turn the energy-removable layer into a porous insulating layer.

A method includes forming a first dielectric layer over a source/drain region, and forming a source/drain contact plug over and electrically connecting to the source/drain region. A top portion of the source/drain contact plug has a first lateral dimension. An implantation process is performed to implant a dopant into the first dielectric layer. The implantation process results in the source/drain contact plug to have a second lateral dimension smaller than the first lateral dimension. The method further includes forming a second dielectric layer over the etch stop layer, and forming a gate contact plug adjacent to the source/drain contact plug.

The present disclosure provides a method to enlarge the process window for forming a source/drain contact. The method may include receiving a workpiece that includes a source/drain feature exposed in a source/drain opening defined between two gate structures, conformally depositing a dielectric layer over sidewalls of the source/drain opening and a top surface of the source/drain feature, anisotropically etching the dielectric layer to expose the source/drain feature, performing an implantation process to the dielectric layer, and after the performing of the implantation process, performing a pre-clean process to the workpiece. The implantation process includes a non-zero tilt angle.

The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.

The present disclosure relates to a method of fabricating a semiconductor structure, the method includes forming an opening and depositing a metal layer in the opening. The depositing includes performing one or more deposition cycles, wherein each deposition cycle includes flowing a first precursor into a deposition chamber and performing an ultraviolet (UV) radiation process on the first precursor. The method further includes performing a first purging process in the deposition chamber to remove at least a portion of the first precursor, flowing a second precursor into the deposition chamber, and purging the deposition chamber to remove at least a portion of the second precursor.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a porous insulating layer positioned above the substrate, a first conductive feature positioned in the porous insulating layer, and covering liners including two top segments and two side segments. The two side segments are positioned on sidewalls of the first conductive feature, and the two top segments are positioned on top surfaces of the porous insulating layer.

Embodiments of 3D memory devices having staircase structures and methods for forming the same are disclosed. In an example, the 3D memory device includes a memory array structure and a staircase structure. The staircase structure is located in an intermediate of the memory array structure and divides the memory array structure into a first memory array structure and a second memory array structure along a lateral direction. The staircase structure includes a plurality of stairs extending along the lateral direction, and a bridge structure in contact with the memory array structure. The stairs include a stair above one or more dielectric pairs. The stair includes a conductor portion electrically connected to the bridge structure and is electrically connected to the memory array structure through the bridge structure. Along a second lateral direction perpendicular to the lateral direction and away from the bridge structure, a width of the conductor portion decreases.