Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.

A method for fabricating a semiconductor device includes forming a line structure including a first contact plug on a semiconductor substrate and a conductive line on the first contact plug, forming a low-k layer having a first low-k, which covers a top surface and side walls of the line structure, performing a converting process on the low-k layer to form a non-converting portion adjacent to side walls of the first contact plug and maintains the first low-k and a converting portion adjacent to side walls of the conductive line and having a second low-k that is lower than the first low-k, and forming a second contact plug which is adjacent to the first contact plug with the non-converting portion therebetween while being adjacent to the conductive line with the converting portion therebetween.

The present disclosure relates to an integrated chip including a lower conductive wire within a first dielectric layer over a substrate. A second dielectric layer is over the first dielectric layer. A conductive via is over the lower conductive wire and within the second dielectric layer. A conductive liner layer lines sidewalls of the via. A barrier layer lines sidewalls of the conductive liner layer and lines sidewalls of the second dielectric layer. The conductive liner layer is laterally separated from the second dielectric layer by the barrier layer. The conductive liner layer vertically extends between sidewalls of the barrier layer from a bottom surface of the conductive via to a top surface of the lower conductive wire.

A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first metal layer formed over a substrate and a dielectric layer formed over the first metal layer. The semiconductor device structure further includes an adhesion layer formed in the dielectric layer and over the first metal layer and a second metal layer formed in the dielectric layer. The second metal layer is electrically connected to the first metal layer, and a portion of the adhesion layer is formed between the second metal layer and the dielectric layer. The adhesion layer includes a first portion lining with a top portion of the second metal layer, and the first portion has an extending portion along a vertical direction.

Interconnect structures exhibiting reduced accumulation of copper vacancies along interfaces between contact etch stop layers (CESLs) and interconnects, along with methods for fabrication, are disclosed herein. A method includes forming a copper interconnect in a dielectric layer and depositing a metal nitride CESL over the copper interconnect and the dielectric layer. An interface between the metal nitride CESL and the copper interconnect has a first surface nitrogen concentration, a first nitrogen concentration and/or a first number of nitrogen-nitrogen bonds. A nitrogen plasma treatment is performed to modify the interface between the metal nitride CESL and the copper interconnect. The nitrogen plasma treatment increases the first surface nitrogen concentration to a second surface nitrogen concentration, the first nitrogen concentration to a second nitrogen concentration, and/or the first number of nitrogen-nitrogen bonds to a second number of nitrogen-nitrogen bonds, each of which minimizes accumulation of copper vacancies at the interface.

There is provided a semiconductor device including an etching stop film which is placed disposed on a substrate; an interlayer insulating film which is disposed on the etching stop film; a trench which penetrates the interlayer insulating film and the etching stop film; a spacer which extends along side walls of the trench; a barrier film which extends along the spacer and a bottom surface of the trench; and a filling film which fills the trench on the barrier film. The trench includes a first trench and a second trench which are spaced apart from each other in a first direction and have different widths from each other in the first direction. A bottom surface of the second trench is placed disposed below a bottom surface of the first trench.

A semiconductor device includes an etching stop film disposed on a substrate; an interlayer insulating film on the etching stop film; a first trench and a second trench which are spaced apart in a first direction, and penetrate the etching stop film and the interlayer insulating film, the first trench having a side wall that exposes the interlayer insulating film, and the second trench having a side wall that exposes the interlayer insulating film; a first spacer which covers the interlayer insulating film exposed by the side wall of the first trench and does not cover a portion of the side wall of the first trench; a second spacer which covers the interlayer insulating film exposed by the side wall of the second trench and does not cover a portion of the side wall of the second trench; a first barrier layer which extends along a side wall of the first spacer, the portion of the side wall of the first trench not covered by the first spacer, and a bottom surface of the first trench; a first filling film which fills the first trench, on the first barrier layer; a second barrier layer which extends along a side wall of the second spacer, the portion of the side wall of the second trench not covered by the second spacer, and a bottom surface of the second trench; and a second filling film which fills the second trench on the second barrier layer. I In the first direction, a width of the first trench and a width of the second trench are different from each other, and at a first height from a bottom surface of the substrate, a thickness of the first spacer on the side wall of the first trench is different from a thickness of the second spacer on the side wall of the second trench.

A nitrogen plasma treatment is used on an adhesion layer of a contact plug. As a result of the nitrogen plasma treatment, nitrogen is incorporated into the adhesion layer. When a contact plug is deposited in the opening, an interlayer of a metal nitride is formed between the contact plug and the adhesion layer. A nitrogen plasma treatment is used on an opening in an insulating layer. As a result of the nitrogen plasma treatment, nitrogen is incorporated into the insulating layer at the opening. When a contact plug is deposited in the opening, an interlayer of a metal nitride is formed between the contact plug and the insulating layer.

The present disclosure provides a method for fabricating a semiconductor structure, including forming an inter dielectric layer over a first region and a second region of a substrate, wherein the second region is adjacent to the first region, forming a high-k material over the inter dielectric layer in the first region and the second region, forming an oxygen capturing layer over the high-k material in the first region, and applying oxidizing agent over the oxygen capturing layer.

Films are modified to include deuterium in an inductive high density plasma chamber. Chamber hardware designs enable tunability of the deuterium concentration uniformity in the film across a substrate. Manufacturing of solid state electronic devices include integrated process flows to modify a film that is substantially free of hydrogen and deuterium to include deuterium.