Disclosed is a method for manufacturing a contact hole, a semiconductor structure and electronic equipment. The method includes: forming a mask layer on an upper end face of a first oxide layer of the semiconductor structure, and exposing a pattern of a target contact hole on the mask layer; exposing a portion, corresponding to a target contact hole, of an upper end face of a contact layer and a portion, corresponding to the target contact hole, of an upper end face of an upper layer structure; depositing a second insulation layer on an etched surface, and depositing a second oxide layer on the second insulation layer; and removing portions, above the upper end face of the first oxide layer, of the second insulation layer and the second oxide layer, and removing a part of the contact layer, and exposing an upper end face of a zeroth layer contact.

A method of forming a semiconductor device includes providing a substrate having a patterned film including manganese; depositing a graphene layer over exposed surfaces of the patterned film; depositing a dielectric layer containing silicon and oxygen over the graphene layer; and heat-treating the substrate to form a manganese-containing diffusion barrier region between the graphene layer and the dielectric layer.

A microelectronic device, including a stack structure including alternating conductive structures and dielectric structures is disclosed. Memory pillars extend through the stack structure. Contacts are laterally adjacent to the memory pillars and extending through the stack structure. The contacts including active contacts and support contacts. The active contacts including a liner and a conductive material. The support contacts including the liner and a dielectric material. The conductive material of the active contacts is in electrical communication with the memory pillars. Methods and electronic systems are also disclosed.

Semiconductor device and fabrication method are provided. The method for forming the semiconductor device includes providing a substrate; forming a dielectric layer on the substrate; forming a through hole in the dielectric layer, the through hole exposing a portion of a top surface of the substrate; performing a surface treatment process on the dielectric layer of sidewalls of the through hole; and filling a metal layer in the through hole.

In one exemplary aspect, a method comprises providing a semiconductor structure having a substrate, one or more first dielectric layers over the substrate, a first metal plug in the one or more first dielectric layers, and one or more second dielectric layers over the one or more first dielectric layers and the first metal plug. The method further comprises etching a via hole into the one or more second dielectric layers to expose the first metal plug, etching a top surface of the first metal plug to create a recess thereon, and applying a metal corrosion protectant comprising a metal corrosion inhibitor to the top surface of the first metal plug.

A method for forming a semiconductor structure includes the following operations. A substrate is provided, and the substrate includes an active surface and a back surface opposite to the active surface. An etching stop layer is formed on the back surface of the substrate. The substrate is fixed onto a first temporary carrier to make the etching stop layer be located between the substrate and the first temporary carrier. The substrate is etched until reaching the etching stop layer to form a via structure penetrating through the substrate.

An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, and a second conductive feature disposed over the first conductive feature. The second conductive feature includes a first sidewall, a first bottom, and a first angle between the first sidewall and the first bottom. The structure further includes a third conductive feature disposed over the dielectric layer and adjacent the second conductive feature. The third conductive feature includes a second sidewall, a second bottom, and a second angle between the second sidewall and the second bottom, the second angle is substantially different from the first angle, and the second and third conductive features are partially overlapping in an axis substantially parallel to a major surface of the substrate.

A method for forming conductive lines comprises forming a hardmask on an insulator layer, a planarizing layer on the hardmask, and a hardmask on the planarizing layer, removing exposed portions of a layer of sacrificial mandrel material to form first and second sacrificial mandrels on the hardmask, and depositing a layer of spacer material in the gap, and over exposed portions of the first and second sacrificial mandrels and the hardmask. Portions of the layer of spacer material are removed to expose the first and second sacrificial mandrels. A filler material is deposited between the first and second sacrificial mandrels. A portion of the filler material is removed to expose the first and second sacrificial mandrels. Portions of the layer of spacer material are removed to expose portions of the hardmask. A trench is formed in the insulator layer, and the trench is filled with a conductive material.

A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film;

a first conductive body contacting the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a side surface of the projecting part contacting an upper surface of the one of the first conductive films.

An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls of the first opening. One or more etch processes form one or more spacer-shaped structures along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.