A method includes forming a trench in a semiconductor layer of a device wafer and depositing a liner on the trench sidewalls. The liner is removed from the trench bottom, and the trench is deepened anisotropically to form an extension fully along the trench, or locally by applying a mask. The semiconductor material is removed outwardly from the extension by etching to create a cavity wider than the trench and below the liner. A space formed by the trench and cavity is filled with electrically conductive material to form a buried interconnect rail comprising a narrow portion in the trench and a wider portion in the cavity. The wider portion can be contacted by a TSV connection, enabling a contact area between the connection and buried rail. The etching forms a wider rail portion at a location remote from active devices formed on the front surface of the semiconductor layer.

A semiconductor device includes a first gate structure and a second gate structure over a fin, a dielectric cut pattern sandwiched by the first and second gate structures, and a liner layer surrounding the dielectric cut pattern. The dielectric cut pattern is spaced apart from the fin and extends further from the substrate than a first gate electrode of the first gate structure and a second gate electrode of the second gate structure. The semiconductor device further includes a conductive feature sandwiched by the first and second gate structures. The conductive feature is divided by the conductive feature into a first segment and a second segment. The first segment of the conductive feature is above a source/drain region of the fin.

A transistor structure includes a semiconductor substrate, a gate structure, a channel region, and a first conductive region. The semiconductor substrate has a semiconductor surface. The gate structure is above the semiconductor surface, and a first concave is formed to reveal the gate structure. The channel region is under the semiconductor surface. The first conductive region is electrically coupled to the channel region, and a second concave is formed to reveal the first conductive region. A mask pattern in a photolithography process is used to define the first concave, and the mask pattern only defines one dimension length of the first concave.

A method for fabricating a semiconductor device includes: forming a stack body over a substrate; forming channel structures in the stack body, the channel structures comprising a channel layer penetrating the stack body; forming a contact-level dielectric layer over the stack body and the channel structures; forming a contact hole penetrating the contact-level dielectric layer; forming contact plugs in the contact hole, the contact plugs coupled to the channel layers of the channel structures; recessing the contact plugs to form upper surfaces of the contact plugs that are lower than an upper surface of the contact-level dielectric layer; forming a bit line-level dielectric layer including a spacer layer over the recessed contact plugs; etching the bit line-level dielectric layer to form trenches that expose the recessed contact plugs; and forming a bit line in one or more of the trenches.

A method of forming a semiconductor transistor device. The method comprises forming a fin-shaped channel structure over a substrate and forming a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite endings of the fin structure. The method further comprises forming a metal gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain epitaxial structure and the second source/drain epitaxial structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.

Metal-insulator-metal (MIM) capacitor, an integrated semiconductor device having a MIM capacitor and methods of making. The MIM capacitor includes a first metal layer, a second metal layer and a dielectric layer located between the second metal layer and the first metal layer. The first metal layer, the second metal layer and the dielectric layer may be formed in a comb structure, wherein the comb structure include a first tine structure and at least a second tine structure.

The present disclosure relates to an integrated chip including a semiconductor device. The semiconductor device includes a first source/drain structure, a second source/drain structure, a stack of channel structures, and a gate structure. The stack of channel structures and the gate structure are between the first and second source/drain structures. The gate structure surrounds the stack of channel structures. A first conductive wire overlies and is spaced from the semiconductor device. The first conductive wire includes a first stack of conductive layers. A first conductive contact extends through a dielectric layer from the first conductive wire to the first source/drain structure. The first conductive contact is on a back-side of the first source/drain structure.

A semiconductor processing tool performs passivation layer deposition and removal in situ. A transport mechanism included in the semiconductor processing tool transfers a semiconductor structure through different deposition chambers (e.g., without breaking or removing a vacuum environment). Accordingly, the semiconductor processing tool deposits a target layer that is thinner on, or even absent from, a metal layer, such that contact resistance is reduced between a conductive structure formed over the target layer and the metal layer. As a result, electrical performance of a device including the conductive structure is improved. Moreover, because the process is performed in situ (e.g., without breaking or removing the vacuum) in the semiconductor processing tool, production time and risk of impurities in the conductive structure are reduced. As a result, throughput is increased, and chances of spoiled wafers are decreased.

A method of manufacturing an integrated circuit device including a self-aligned air spacer including the operations of forming a dummy gate, forming a sidewall on the dummy gate, forming a dummy layer on the sidewall, constructing a gate structure within an opening defined by the sidewall, removing at least a portion of the first dummy layer to form a first recess between the sidewall layer and the dummy gate, and capping the first recess to form a first air spacer.

Provided are semiconductor and a method for manufacturing semiconductor. The semiconductor structure includes: a substrate and a gate located on the substrate, a source is formed in the substrate on one side of the gate, and a drain is formed in the substrate on another side of the gate; a dielectric layer covering a surface of the gate; a contact structure passing through the dielectric layer and electrically connected to the source or the drain, the contact structure including a stack of a first contact layer and a second contact layer, and in a direction from the source to the drain, a width of the second contact layer being greater than a width of the first contact layer; and an electrical connection layer located at a top surface of the dielectric layer and in contact with part of a top surface of the second contact layer.