Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes contacting a liner that is disposed adjacent to a porous interlayer dielectric (ILD) layer of dielectric material with a selectively reactive gas at reaction conditions. A portion of the liner is reacted with the selectively reactive gas to form a converted expanded portion that is disposed between a remaining portion of the liner and the porous ILD layer.

Reducing liner corrosion during metallization of semiconductor devices at BEOL includes providing a starting metallization structure, the structure including a bottom layer of dielectric material with a via therein, a liner lining the via and extending over upper edges thereof, the lined via over filled with a conductive material, recessing the conductive material down to the liner, further selectively recessing the conductive material below the upper edges of the via without damaging the liner, and forming a cap of the liner material on the conductive material.

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; forming a silicon layer on the substrate to cover the gate structure entirely; planarizing the silicon layer; and performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate.

Implementations of the present disclosure provide methods for preventing contact damage or oxidation after via/trench opening formation. In one example, the method includes forming an opening in a structure on the substrate to expose a portion of a surface of an electrically conductive feature, and bombarding a surface of a mask layer of the structure using energy species formed from a plasma to release reactive species from the mask layer, wherein the released reactive species form a barrier layer on the exposed surface of the electrically conductive feature.

Reducing liner corrosion during metallization of semiconductor devices at BEOL includes providing a starting metallization structure, the structure including a bottom layer of dielectric material with a via therein, a liner lining the via and extending over upper edges thereof, the lined via over filled with a conductive material, recessing the conductive material down to the liner, further selectively recessing the conductive material below the upper edges of the via without damaging the liner, and forming a cap of the liner material on the conductive material.

An interconnect structure for integrated circuits for copper wires in integrated circuits and methods for making the same are provided. Mn, Cr, or V containing layer forms a barrier against copper diffusing out of the wires, thereby protecting the insulator from premature breakdown, and protecting transistors from degradation by copper. The Mn, Cr, or V containing layer also promotes strong adhesion between copper and insulators, thus preserving the mechanical integrity of the devices during manufacture and use, as well as protecting against failure by electromigration of the copper during use of the devices and protecting the copper from corrosion by oxygen or water from its surroundings. In forming such integrated circuits, certain embodiments of the invention provide methods to selectively deposit Mn, Cr, V, or Co on the copper surfaces while reducing or even preventing deposition of Mn, Cr, V, or Co on insulator surfaces. Catalytic deposition of copper using a Mn, Cr, or V containing precursor and an iodine or bromine containing precursor is also provided.

A power semiconductor component includes a power semiconductor partial structure having an insulating layer arranged on an upper side of a semiconductor body. A contact hole arranged on an upper side of the insulating layer proceeds from that side, extending at least partly within the insulating layer. An adhesion promoter layer arranged on an upper side of the power semiconductor partial structure at least partly covers the insulating layer upper side and a surface of the contact hole. A tungsten-comprising layer arranged on the adhesion promoter layer at least partly covers the adhesion promoter layer and has a first thickness in a region of the contact hole and dimensioned such that the tungsten-comprising layer fills the contact hole. The tungsten-comprising layer has a second thickness in the region of the insulating layer upper side which is less than the first thickness. A connection layer is arranged on the tungsten-comprising layer.

Interconnect structures and methods and apparatuses for forming the same are disclosed. In an embodiment, a method includes supplying a process gas to a process chamber; igniting the process gas into a plasma in the process chamber; reducing a pressure of the process chamber to less than 0.3 mTorr; and after reducing the pressure of the process chamber, depositing a conductive layer on a substrate in the process chamber.

A method for producing a power semiconductor component includes: providing a power semiconductor partial structure having an insulating layer arranged on an upper side of a semiconductor body and a contact hole proceeding from an upper side of the insulating layer, extending at least partly within the insulating layer and configured for electrical contacting of a contact region below the upper side; at least partly covering the upper side and a surface of the contact hole with an adhesion promoter layer; at least partly covering the adhesion promoter layer with a tungsten-comprising layer having a first thickness dimensioned such that the tungsten-comprising layer fills the contact hole; removing part of the tungsten-comprising layer in a region of the upper side such that the tungsten-comprising layer has a second thickness in the upper side region that is less than the first thickness; and applying a connection layer to the tungsten-comprising layer.