A semiconductor structure including a first metal line and a second metal line in a dielectric layer, the first metal line and the second metal line are adjacent and within the same dielectric level; an air gap structure in the dielectric layer and between the first metal line and the second metal line, wherein the air gap structure includes an air gap oxide layer and an air gap; and a barrier layer between the air gap structure and the first metal line, wherein the barrier layer is an oxidized metal layer.

A method of forming a titanium nitride (TiN) diffusion barrier includes exposing a deposition surface to a first pulse of a titanium-containing precursor and to a first pulse of a nitrogen-rich plasma to form a first TiN layer with a first nitrogen concentration making a lower portion of the TiN diffusion barrier, the first nitrogen concentration of the first TiN layer is increased by the first pulse of the nitrogen-rich plasma reducing a reactivity of the lower portion of the TiN diffusion barrier to prevent fluorine diffusion. The first TiN layer is exposed to second pulses of the titanium-containing precursor and the nitrogen-rich plasma to form a second TiN layer with a second nitrogen concentration above the first TiN layer making an upper portion of the TiN diffusion barrier, the first pulse of the nitrogen-rich plasma has a substantially longer duration than the second pulse of the nitrogen-rich plasma.

A nitrogen plasma treatment is used on an adhesion layer of a contact plug. As a result of the nitrogen plasma treatment, nitrogen is incorporated into the adhesion layer. When a contact plug is deposited in the opening, an interlayer of a metal nitride is formed between the contact plug and the adhesion layer. A nitrogen plasma treatment is used on an opening in an insulating layer. As a result of the nitrogen plasma treatment, nitrogen is incorporated into the insulating layer at the opening. When a contact plug is deposited in the opening, an interlayer of a metal nitride is formed between the contact plug and the insulating layer.

A plating method can improve adhesivity with a substrate. The plating method of performing a plating process on the substrate includes forming a vacuum-deposited layer 2A on the substrate 2 by performing a vacuum deposition process on the substrate 2; forming an adhesion layer 21 and a catalyst adsorption layer 22 on the vacuum-deposited layer 2A of the substrate 2; and forming a plating layer stacked body 23 having a first plating layer 23a and a second plating layer 23b which function as a barrier film on the catalyst adsorption layer 22 of the substrate 2. By forming the vacuum-deposited layer 2A, a surface of the substrate 2 can be smoothened, so that the vacuum-deposited layer 2A serving as an underlying layer can improve the adhesivity.

A method of manufacturing a semiconductor device may include: forming an opening in a dielectric layer, the opening exposing a non-conductive layer disposed over a semiconductor substrate; forming a self-assembled monolayer (SAM) within the opening and over the non-conductive layer; forming a catalytic layer within the opening and over the SAM; filling the opening having the SAM and the catalytic layer with a conductive material to form a plug; and forming a barrier layer on sidewalls of the plug.

Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects with improved adhesion are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a metal interconnect material directly over and contacting a top surface of the dielectric matrix, wherein the metal interconnect material fills the set of trenches and the set of vias; depositing a barrier layer over a top surface of the device; annealing the barrier layer to diffuse the barrier layer to a bottom surface of the metal interconnect material; planarizing a top surface of the intermediate semiconductor interconnect device; and depositing a dielectric cap over the intermediate semiconductor interconnect device.

A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.

A semiconductor device includes providing a workpiece including an insulating material layer disposed thereon. The insulating material layer includes a trench formed therein. A barrier layer on the sidewalls of the trench is formed using a surface modification process and a surface treatment process.

Embodiments herein relate to a package using aluminum oxide as an adhesion and high-thermal conductivity layer with a buildup layer having a first side and a second side opposite the first side, a first trace applied to the first side of the buildup layer, an aluminum oxide layer coupled with the first trace and an exposed area of the first side of the buildup layer, a lamination buildup layer coupled with the aluminum oxide layer on a side of the aluminum oxide layer opposite the buildup layer, wherein the lamination buildup layer includes one or more vias to the trace, and a seed layer coupled with the lamination buildup layer. Other embodiments may be described and/or claimed.

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a conductive line over the semiconductor substrate. The conductive line has a barrier region surrounding an inner portion of the conductive line, and the barrier region has a greater dopant concentration than the inner portion. The semiconductor device structure also includes a conductive via on the conductive line. The semiconductor device structure further includes a dielectric layer over the semiconductor substrate. The dielectric layer surrounds the conductive line and the conductive via.