One illustrative method disclosed herein includes, among other things, forming a first trench and a second trench in a layer of insulating material, the first trench having a first lateral critical dimension, the second trench having a second lateral critical dimension that is greater than the first lateral critical dimension of the first trench, forming a first conductive structure in the first trench, wherein a first bulk metal material constitutes a bulk portion of the first conductive structure, and forming a second conductive structure in the second trench, wherein a second bulk metal material constitutes a bulk portion of the second conductive structure and wherein the first bulk metal material and second bulk metal material are different materials.

A method of filling structures on a substrate uses a semi-dynamic reflow process. The method may include depositing a metallic material on the substrate at a first temperature, heating the substrate to a second temperature higher than the first temperature wherein heating of the substrate causes a static reflow of the deposited metallic material on the substrate, stopping heating of the substrate, and depositing additional metallic material on the substrate causing a dynamic reflow of the deposited additional metallic material on the substrate. RF bias power may be applied during the dynamic reflow to facilitate in maintaining the temperature of the substrate.

A method of manufacturing a semiconductor device comprises providing a substrate; forming an insulating layer on the substrate; etching the insulating layer to form an opening that exposes the substrate; forming a contact plug in the opening and on the insulating layer; forming a metal layer on the contact plug; and irradiating the metal layer with a laser.

Some examples of the present disclosure provide a method for manufacturing a wire layer. The method for manufacturing a wire layer includes steps in which a wafer having an opening is provided; conductive grains are deposited on the wafer, and on a bottom and a side wall of the opening to form a conductive film, during which a temperature of a surface of the wafer is lower than a flowing temperature of the conductive film, and when the temperature of the surface of the wafer is greater than or equal to the flowing temperature, the conductive film starting to flow; and after the conductive film is formed, the temperature of the surface of the wafer is elevated to perform a reflowing process, such that the conductive film is converted to a conductive layer filling up the opening.

Embodiments of the present disclosure are related to improved methods for forming an interconnect structure in a substrate. In one implementation, the method includes providing a substrate comprising a metal region and a dielectric region surrounding the metal region, selectively forming a cobalt-containing alloy cap layer on the metal region by exposing the substrate to a first precursor and a second precursor, the first precursor and the second precursor are selected from a group consisting of an aluminum-containing precursor, a cobalt-containing precursor, a ruthenium-containing precursor, a manganese-containing precursor, and a tungsten-containing precursor, wherein the first precursor is different from the second precursor.

An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. Other embodiments are described herein.

Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having stepped top vias that reduce via resistance. In a non-limiting embodiment of the invention, a surface of a conductive line is recessed below a first dielectric layer. A second dielectric layer is formed on the recessed surface and an etch stop layer is formed over the structure. A first cavity is formed that exposes the recessed surface of the conductive line and sidewalls of the second dielectric layer. The first cavity includes a first width between sidewalls of the etch stop layer. The second dielectric layer is removed to define a second cavity having a second width greater than the first width. A stepped top via is formed on the recessed surface of the conductive line. The top via includes a top portion in the first cavity and a bottom portion in the second cavity.

Provided is a technique of forming an aluminum film that has high flatness and less cavities. Step S11 is forming a first film having a thickness that is equal to or greater than 0.1 μm and less than 1 μm, by sputtering a material onto a substrate. Step S12 is reflowing the first film by heating the first film. Step S13 is forming a second film by sputtering the material onto the first film that has been reflowed. Step S14 is reflowing the second film by heating the second film. Step S15 is forming a third film by sputtering the material onto the second film that has been reflowed. Step S16 is reflowing the third film by heating the third film.

A magnetically enhanced low temperature high density plasma chemical vapor deposition (LT-HDP-CVD) source has a hollow cathode target and an anode, which form a gap. A cathode target magnet assembly forms magnetic field lines substantially perpendicular to the cathode surface. A gap magnet assembly forms a magnetic field in the gap that is coupled with the cathode target magnetic field. The magnetic field lines cross the pole piece electrode positioned in the gap. The pole piece is isolated from ground and can be connected to a voltage power supply. The pole piece can have negative, positive, floating, or RF electrical potentials. By controlling the duration, value, and sign of the electric potential on the pole piece, plasma ionization can be controlled. Feed gas flows through the gap between the hollow cathode and anode. The cathode can be connected to a pulse power or RF power supply, or cathode can be connected to both power supplies. The cathode target and substrate can be inductively grounded.

Disclosed are a silicon wafer and a method for filling a silicon via thereof, and belong to the field of superconducting quantum technologies. The method includes: obtaining a silicon wafer including at least one silicon via; providing a superconducting material on at least one side of the silicon wafer, the at least one side comprising a side where an opening of the silicon via is located; and heating and pressurizing the superconducting material to fill the superconducting material into the silicon via.