The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.

The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.

Embodiments provide a polishing composition for a semiconductor process facilitating the formation of a microcircuit pattern and minimizing the generation of defects and scratches and a method of preparing a polished article using the same.

Embodiments provide a polishing composition for a semiconductor process, in which the absorbance ratio of a group having a specific size of particle diameter compared to the overall average particle size (D.sub.50) is a predetermined ratio or less with respect to the absorbance of a group having a particle diameter more than 0.5 times and 2.5 times or less the overall average particle size.

A semiconductor structure and method for forming a semiconductor structure includes formation of a recess in a metal layer during the fabrication process to provide process improvements and a conductive via with reduced contact resistance. The semiconductor structure includes a dielectric layer, a metal layer, an etch stop layer, and a conductive via. The top surface of the dielectric layer extends above a top surface of the metal layer, and a bottom surface of the conductive via extends below the top surface of the dielectric layer.

Methods and apparatus for processing a substrate are provided. For example, a method includes sputtering a material from a target in a PVD chamber to form a material layer on a layer comprising a feature of the substrate, the feature having an opening width defined by a first sidewall and a second sidewall, the material layer having a greater lateral thickness at the top surface of the layer than a thickness on the first sidewall or the second sidewall within the feature, depositing additional material on the layer by biasing the layer with an RF bias at a low power, etching the material layer from the layer by biasing the layer with an RF bias at a high-power, and repeatedly alternating between the low power and the high-power at a predetermined frequency.

A method for manufacturing a semiconductor structure includes the following operations. A base and a dielectric layer arranged on the base are provided. A first conductive pillar, a second conductive pillar and a third conductive pillar arranged in the dielectric layer are formed. A mask layer is formed. A portion of a thickness of the third conductive pillar is etched by using the third mask layer as a mask to form a third lower conductive pillar and a third upper conductive pillar stacked on one another, in which the third upper conductive pillar, the third lower conductive pillar and the dielectric layer are configured to form at least one groove. A cover layer filling the at least one groove is formed, in which the cover layer exposes the top surface of the third upper conductive pillar.

Embodiments disclosed herein describe semiconductor devices that include semiconductor structures and methods of forming the semiconductor structures. The semiconductor structures may include an upper conductive line, a first lower conductive line laterally insulated by a first lower dielectric region and a second lower dielectric region. The semiconductor structure also includes a lower level via region above the first lower conductive line. The lower level via region includes a dielectric blocking material and a spacer material.

A method of manufacturing a semiconductor structure includes: providing a base and a dielectric layer on the base, the base in an array region being provided with discrete capacitive contact plugs and a first conductive layer being formed on a top surface of the capacitive contact plugs; sequentially forming a conversion layer and a target layer on the first conductive layer and the dielectric layer, the target layer in the array region and the first circuit region being provided with first openings through the target layer; patterning the target layer in the array region as well as in the first circuit region and the second circuit region to form a second opening and a third opening; etching the conversion layer to form a first trench; forming a filling layer filling the first trench and removing the conversion layer to form a second trench filled by a second conductive layer.

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a gate structure being provided on a surface of the substrate, and a source region and a drain region being provided in the substrate at two sides of the gate structure, respectively; and a contact located on the substrate, the contact including a first contact located on the substrate and a second contact located on a side of the first contact away from the substrate, in which an area of a bottom surface of the first contact is greater than an area of a top surface of the second contact.

A semiconductor device includes: a lower wiring including: a lower filling film, which extends in a first direction and includes a first portion having a first width in the first direction and a second portion, having a second width smaller than the first width in the first direction, on the first portion; and a lower barrier film which is disposed on a side wall and a bottom surface of the first portion, and is not disposed on a side wall of the second portion in a cross-sectional view of the first direction; and an upper wiring structure including: an upper via connected to the lower wiring; and an upper wiring extending in a second direction intersecting the first direction on the upper via, wherein the upper wiring structure further includes an upper barrier film, and an upper filling film in a trench defined by the upper barrier film, each of the upper via and the upper wiring comprises the upper barrier film and the upper filling film, and the upper via is not separated from the upper wiring by the upper barrier film, and is separated from the second portion of the lower filling film by the upper barrier film.