Embodiments include transistor devices and a method of forming the transistor devices. A transistor device includes a first dielectric over a substrate, and vias on a first metal layer, where the first metal layer is on an etch stop layer that is on the first dielectric. The transistor device also includes a second dielectric over the first metal layer, vias, and etch stop layer, where the vias include sidewalls, top surfaces, and bottom surfaces, and stacked transistors on the second dielectric and the top surfaces of the vias, where the sidewalls and top surfaces of the vias are positioned within a footprint of the stacked transistors. The stacked transistors include gate electrodes and first and second transistor layers. The first metal layer includes conductive materials including tungsten or cobalt. The footprint may include a bottom surface of the first transistor layer and a bottom surface of the gate electrodes.

A semiconductor device is provided. The semiconductor device includes: a first active pattern extending in a first direction; a second active pattern spaced apart extending in the first direction, the first active pattern being provided between the second active pattern and a substrate; a gate structure extending in a second direction, the first active pattern and the second active pattern passing through the gate structure, and the second direction crossing the first direction; a first source/drain area connected with the first active pattern and provided on a side of the gate structure; a second source/drain area connected with the second active pattern and provided on the first source/drain area; a first insulating structure provided between the substrate and the first source/drain area, the first insulating structure not being provided between the substrate and the gate structure; and a second insulating structure provided between the first source/drain area and the second source/drain area.

A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer and control circuits; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where each of the first memory cells include one first transistor, where each of the second memory cells include one second transistor, where at least one of the first or second transistors has a channel, a source, and a drain having a same doping type.

A method for producing a 3D memory device including: providing a first level including a single crystal layer and control circuits, where the control circuits include a plurality of first transistors; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; performing processing steps to form a plurality of first memory cells within the second level, where each of the first memory cells include one of a plurality of second transistors, where the control circuits include memory peripheral circuits, where at least one first memory cell is at least partially atop a portion of the memory peripheral circuits, and where fabrication processing of the first transistors accounts for a temperature and time associated with processing the second level and the plurality of second transistors by adjusting a process thermal budget of the first level accordingly.

Aspects of the present disclosure provide a semiconductor structure. For example, the semiconductor structure can include a lower channel structure, an upper channel structure formed vertically over the lower channel, a first transistor device including lower and upper gates formed around a first portion of the lower and upper channel structures, respectively, and a separation layer formed between and separating the lower and upper gates, and a second transistor device including a common gate formed around a second portion of the lower and upper channel structures. The first portion of the lower channel structure is equal to the first portion of the upper channel structure in width, and has a first width less than a second width of the second portion of the lower channel structure.

The present technology relates to a semiconductor device and a manufacturing method therefor, a solid-state imaging element and electronic equipment that make it possible to suppress breakdown of a side wall insulating film by charge damage to suppress short-circuiting. The semiconductor device according to an aspect of the present technology includes a first semiconductor substrate on which a given circuit is formed, a second semiconductor substrate, and through electrodes that electrically connect the first semiconductor substrate and the second semiconductor substrate to each other. The through electrode is formed such that a through-hole is opened through a protection diode structure formed in the first semiconductor substrate, an insulating film is deposited on a side wall of the through-hole, and an electrode material is then filled inside the through-hole in which the insulating film is deposited. The present technology can be applied, for example, to a CMOS image sensor.

A semiconductor structure for a DRAM is described having multiple layers of arrays of memory cells. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. The memory cells preferably are thyristors. Methods of fabricating the array are described.

Embodiments herein describe techniques for a semiconductor device including a first transistor stacked above and self-aligned with a second transistor, where a shadow of the first transistor substantially overlaps with the second transistor. The first transistor includes a first gate electrode, a first channel layer including a first channel material and separated from the first gate electrode by a first gate dielectric layer, and a first source electrode coupled to the first channel layer. The second transistor includes a second gate electrode, a second channel layer including a second channel material and separated from the second gate electrode by a second gate dielectric layer, and a second source electrode coupled to the second channel layer. The second source electrode is self-aligned with the first source electrode, and separated from the first source electrode by an isolation layer. Other embodiments may be described and/or claimed.

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second transistors each include at least two side-gates, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.

A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming peripheral circuitry in and/or on the first level, and includes first single crystal transistors; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming second level disposed on top of the second metal layer; performing a first lithography step; forming a third level on top of the second level; performing a second lithography step; processing steps to form first memory cells within the second level and second memory cells within the third level, where the plurality of first memory cells include at least one second transistor, and the plurality of second memory cells include at least one third transistor; and deposit a gate electrode for second and third transistors simultaneously.