An integrated circuit device includes a first-type active-region semiconductor structure, a second-type active-region semiconductor structure stacked with the first-type active-region semiconductor structure, a front-side power rail in a front-side conductive layer, and a back-side power rail in a back-side conductive layer. The integrated circuit device also includes a source conductive segment intersecting the first-type active-region semiconductor structure at a source region of a transistor, a back-side power node in the back-side conductive layer, and a top-to-bottom via-connector. The source conductive segment is conductively connected to the front-side power rail through a front-side terminal via-connector. The top-to-bottom via-connector is connected between the source conductive segment and the back-side power node

A circuit structure includes a substrate that includes a first transistor stack over the substrate that includes: a first transistor where the first transistor is a first conductivity type; and a second transistor, above the first transistor, where the second transistor is a second conductivity type different from the first conductivity type. The structure also includes a plurality of first conductive lines in a first metal layer above the first transistor stack, the plurality of first conductive lines electrically connected to the first transistor stack. The structure also includes a plurality of second conductive lines in a second metal layer below the substrate and underneath the first transistor stack, the plurality of second conductive lines electrically connected to the first transistor stack. The plurality of first conductive lines are configured asymmetrically with respect to the plurality of second conductive lines.

A semiconductor device includes a base isolation layer, a first transistor with a first source electrode at a first side of the base isolation layer. A bridge pillar extends through the base isolation layer, and a metal electrode electrically connects the bridge pillar to the first source electrode. The metal electrode and the first source electrode are at the same side of the base isolation layer. A second metal electrode at an opposite side of the base isolation layer electrically connects to the bridge pillar and to a conductive line at the second side of the base isolation layer.

A semiconductor device includes a first transistor device of a first type. The first transistor includes first nanostructures, a first pair of source/drain structures, and a first gate electrode on the first nanostructures. The semiconductor device also includes a second transistor device of a second type formed over the first transistor device. The second transistor device includes second nanostructures over the first nanostructures, a second pair of source/drain structures over the first pair or source/drain structures, and a second gate electrode on the second nanostructures and over the first nanostructures. The semiconductor device also includes a first isolation structure between the first and second nanostructures. The semiconductor device further includes a second isolation structure in contact with a top surface of the first pair of source/drain structures. The semiconductor device also includes a seed layer between the second isolation structure and the second pair of source/drain structures.

A semiconductor device structure, along with methods of forming such, are described. The structure includes a first gate electrode layer, a second gate electrode layer disposed over and aligned with the first gate electrode layer, and a gate isolation structure disposed between the first gate electrode layer and the second gate electrode layer. The gate isolation structure includes a first surface and a second surface opposite the first surface. At least a portion of the first surface is in contact with the first gate electrode layer. The second surface includes a first material and a second material different from the first material, and at least a portion of the second surface is in contact with the second gate electrode layer.

A semiconductor device structure, along with methods of forming such, are described. The structure includes first and second dielectric features and a first semiconductor layer disposed between the first and second dielectric features. The structure further includes an isolation layer disposed between the first and second dielectric features, and the isolation layer is in contact with the first and second dielectric features. The first semiconductor layer is disposed over the isolation layer. The structure further includes a gate dielectric layer disposed over the isolation layer and a gate electrode layer disposed over the gate dielectric layer. The gate electrode layer has an end extending to a level between a first plane defined by a first surface of the first semiconductor layer and a second plane defined by a second surface opposite the first surface.

The present disclosure describes a semiconductor device and methods for forming the same. The semiconductor device includes a first transistor device of a first type and a second transistor device of a second type. The first transistor device includes first nanostructures, a first pair of source/drain structures, and a first gate structure on the first nanostructures. The second transistor device of a second type is formed over the first transistor device. The second transistor device includes second nanostructures over the first nanostructures, a second pair of source/drain structures over the first pair or source/drain structures, and a second gate structure on the second nanostructures and over the first nanostructures. The semiconductor device further includes a first isolation structure in contact with the first and second nanostructures and a second isolation structure in contact with a top surface of the first pair of source/drain structures.

A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers having a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers. The structure further includes a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers and a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers. The first number of semiconductor layers of the first group of semiconductor layers is different from the second number of semiconductor layers of the third group of semiconductor layers.

A semiconductor device and methods of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure with first and second nanostructured layers on the fin structure, forming a polysilicon structure around the superlattice structure, forming a source/drain opening within the superlattice structure, forming a first conductivity type S/D region within a first portion of the S/D opening, forming an isolation layer on the first conductivity type S/D region and within a second portion of the S/D opening, forming a second conductivity type S/D region on the isolation layer and within a third portion the S/D opening, and replacing the polysilicon structure and the second nanostructured layers with a gate structure that surrounds the first nanostructured layers. Materials of the first and second nanostructured layers are different from each other and the second conductivity type is different from the first conductivity type.

A parallel structure comprising source/drain and channel layers alternately stacked on a substrate, and gate stacks formed around peripheries of the channel layers. Each of the channel layers, the source/drain layers on upper and lower sides of the channel layer, and the gate stack formed around the channel layer, form a semiconductor device. In each semiconductor device, one of the source/drain layers is in contact with a first electrically-conductive channel disposed on an outer periphery of the active region, the other is in contact with a second electrically-conductive channel on the outer periphery of the active region, and the gate stack is in contact with a third electrically-conductive channel disposed on the outer periphery of the active region. The first electrically-conductive channel is common to the semiconductor devices, the second electrically-conductive channel is common to the semiconductor devices, and the third electronically-conductive channel is common to the semiconductor devices.