Manufacturing processes leverage process steps used during CMOS formation to form one or more additional type(s) of devices on the same substrate used for the CMOS formation, and at least partially in parallel with the CMOS formation processes. A first layer of implant wells may be formed at a first depth in a substrate using a first mask, and then a second layer of implant wells may be formed at a second, more shallow depth, using a second mask. CMOS devices that are part of a CMOS platform may be formed using some of the wells, while peripheral devices may be formed using remaining wells.

Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first semiconductor channel member and a second semiconductor channel member over the first semiconductor channel member and a porous dielectric feature that includes silicon and nitrogen. In the semiconductor device, the porous dielectric feature is sandwiched between the first and second semiconductor channel members and a density of the porous dielectric feature is smaller than a density of silicon nitride.

A junction field effect transistor (JFET) structure includes a doped polysilicon gate over a channel region of a semiconductor layer. The doped polysilicon gate has a first doping type. A raised epitaxial source is on the source region of the semiconductor layer and adjacent a first sidewall of the doped polysilicon gate, and has a second doping type opposite the first doping type. A raised epitaxial drain is on the drain region of the semiconductor layer and adjacent a second sidewall of the doped polysilicon gate, and has the second doping type. A doped semiconductor region is within the channel region of the semiconductor layer and extending from the source region to the drain region, and a non-conductive portion of the semiconductor layer is within the channel region to separate the doped semiconductor region from the doped polysilicon gate.

A high-electron-mobility field-effect transistor includes a superposition of first and second layers of semiconductor materials so as to form an electron gas layer and includes a gate stack arranged on the superposition. The gate stack includes a conductive electrode and an element made of p-doped semiconductor material, arranged between the conductive electrode and the superposition. The gate stack includes a first dielectric layer arranged between the conductive electrode and the element made of semiconductor material. The element made of semiconductor material, the first dielectric layer, and the conductive electrode have aligned lateral flanks.

A high-electron-mobility field-effect transistor includes a superposition of first and second layers of semiconductor materials so as to form an electron gas layer and includes a gate stack arranged on the superposition. The gate stack includes a conductive electrode and an element made of p-doped semiconductor material, arranged between the conductive electrode and the superposition. The gate stack includes a first dielectric layer arranged between the conductive electrode and the element made of semiconductor material. The element made of semiconductor material, the first dielectric layer, and the conductive electrode have aligned lateral flanks.

A device integrated with JFET, the device is divided into a JFET region and a power device region, and the device includes: a drain (201) with a first conduction type; and a first conduction type region disposed on a front surface of the drain (201); the JFET region includes: a first well (205) with a second conduction type and formed in the first conduction type region; a second well (207) with a second conduction type and formed in the first conduction type region; a JFET source (212) with the first conduction type; a metal electrode formed on the JFET source (212), which is in contact with the JFET source (212); and a second conduction type buried layer (203) formed under the JFET source (212) and the second well (207).

A device integrated with JFET, the device is divided into a JFET region and a power device region, and the device includes: a drain (201) with a first conduction type; and a first conduction type region disposed on a front surface of the drain (201); the JFET region includes: a first well (205) with a second conduction type and formed in the first conduction type region; a second well (207) with a second conduction type and formed in the first conduction type region; a JFET source (212) with the first conduction type; a metal electrode formed on the JFET source (212), which is in contact with the JFET source (212); and a second conduction type buried layer (203) formed under the JFET source (212) and the second well (207).

Methods for processing a semiconductor transistor are provided, where the semiconductor transistor includes a substrate, an epitaxial layer, and transistor components that are formed on the epitaxial layer. The method includes: removing a portion of the substrate that is disposed below a portion of the transistor components, to thereby expose a portion of a bottom surface of the epitaxial layer; forming an electrically insulating layer on the exposed portion of the bottom surface of the epitaxial layer; forming a via that extends from a bottom surface of the insulating layer to a bottom surface of one of the transistor components; depositing at least one metal layer on the bottom surface of the insulating layer, on a side wall of the via and on the bottom surface of one of the transistor components; and applying a solder paste to a bottom surface of the at least one metal layer.

Methods for processing a semiconductor transistor are provided, where the semiconductor transistor includes a substrate, an epitaxial layer, and transistor components that are formed on the epitaxial layer. The method includes: removing a portion of the substrate that is disposed below a portion of the transistor components, to thereby expose a portion of a bottom surface of the epitaxial layer; forming an electrically insulating layer on the exposed portion of the bottom surface of the epitaxial layer; forming a via that extends from a bottom surface of the insulating layer to a bottom surface of one of the transistor components; depositing at least one metal layer on the bottom surface of the insulating layer, on a side wall of the via and on the bottom surface of one of the transistor components; and applying a solder paste to a bottom surface of the at least one metal layer.

In a gate last metal gate process for forming a transistor, a dielectric layer is formed over an intermediate transistor structure, the intermediate structure including a dummy gate electrode, typically formed of polysilicon. Various processes, such as patterning the polysilicon, planarizing top layers of the structure, and the like can remove top portions of the dielectric layer, which can result in decreased control of gate height when a metal gate is formed in place of the dummy gate electrode, decreased control of fin height for finFETs, and the like. Increasing the resistance of the dielectric layer to attack from these processes, such as by implanting silicon or the like into the dielectric layer before such other processes are performed, results in less removal of the top surface, and hence improved control of the resulting structure dimensions and performance.