A semiconductor device including: a first structure including: a first semiconductor pattern protruding from a substrate, the first semiconductor pattern being a channel; a first conductive pattern surrounding the first semiconductor pattern, the first conductive pattern being a gate electrode; a first impurity region under the first semiconductor pattern, the first impurity region contacting the first semiconductor pattern, the first impurity region being a source or drain region; and a second impurity region contacting the first semiconductor pattern, the second impurity region being the other of the source or drain region; and a second structure including: second semiconductor patterns spaced apart from each other, each of the second semiconductor patterns protruding from the substrate; second conductive patterns surrounding the second semiconductor patterns, respectively; and first contact plugs connected to the second conductive patterns, wherein the first structure is a vfet, and the second structure includes a resistor or a capacitor.

A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.

Provided are a CMOS structure, and fabrication methods of a FinFET CMOS, an FD CMOS and a GAA CMOS. The CMOS structure includes an nMOS and a pMOS, The nMOS includes a first channel region and a first gate electrode formed on a semiconductor substrate, and the pMOS includes a second channel region and a second gate electrode formed on the semiconductor substrate, where the first channel region and the second channel region are formed of semiconductor materials with the same conductivity type, and the first gate electrode and the second gate electrode are formed of the conductive materials with the same work function. This CMOS structure reduces the processing steps for fabricating the CMOS, thereby reducing the process complexity and the production cost, which is beneficial for improving the performance and reliability of CMOS and its integrated circuits.

A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a first dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the first dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the first dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

Disclosed herein are stacked transistors with dielectric between channel materials, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein a dielectric material is between channel materials of adjacent strata, and the dielectric material is surrounded by a gate dielectric.

A method of forming a semiconductor structure includes forming a plurality of fins over a substrate, at least a portion of one or more of the fins providing one or more channels for one or more fin field-effect transistors. The method also includes forming a plurality of active gate structures over the fins, forming at least one single diffusion break trench between a first one of the active gate structures and a second one of the active gate structures, and forming at least one double diffusion break trench between a third one of the active gate structures and a fourth one of the active gate structures. The double diffusion break trench has a stepped height profile in the substrate, the stepped height profile comprising a first depth with a first width and a second depth less than the first depth with a second width greater than the first width.

A method includes forming a fin structure on the substrate, wherein the fin structure includes a first fin active region; a second fin active region; and an isolation feature separating the first and second fin active regions; forming a first gate stack on the first fin active region and a second gate stack on the second fin active region; performing a first recessing process to a first source/drain region of the first fin active region by a first dry etch; performing a first epitaxial growth to form a first source/drain feature on the first source/drain region; performing a fin sidewall pull back (FSWPB) process to remove a dielectric layer on the second fin active region; and performing a second epitaxial growth to form a second source/drain feature on a second source/drain region of the second fin active region.

Certain aspects of the present disclosure are directed to a semiconductor device. The semiconductor device generally includes a substrate, at least one silicon-on-insulator (SOI) transistor disposed above the substrate, a gate-all-around (GAA) transistor disposed above the substrate, and a fin field-effect transistor (FinFET) disposed above the substrate.

The present disclosure provides a semiconductor device with improved element performance and reliability. The semiconductor device includes a lower insulating layer, a fin-shaped insulating layer that is on the lower insulating layer and extends in a first direction, a field insulating layer that is on the lower insulating layer and extends in the first direction, a plurality of gate structures that are on the fin-shaped insulating layer and include a gate electrode intersecting the fin-shaped insulating layer, a source/drain region that is on the fin-shaped insulating layer and is between the gate structures, and an active pattern that is on the fin-shaped insulating layer and penetrates the gate electrode and is electrically connected to the source/drain region, where the gate electrode extends in a second direction intersecting the first direction.

A semiconductor structure, including: a base substrate; an insulating layer on the base substrate, the insulating layer having a thickness between about 5 nm and about 100 nm; and an active layer comprising at least two pluralities of different volumes of semiconductor material comprising silicon, germanium, and/or silicon germanium, the active layer disposed over the insulating layer, the at least two pluralities of different volumes of semiconductor material comprising: a first plurality of volumes of semiconductor material having a tensile strain of at least about 0.6%; and a second plurality of volumes of semiconductor material having a compressive strain of at least about −0.6%. Also described is a method of preparing a semiconductor structure and a segmented strained silicon on insulator device.