A semiconductor structure is provided. The semiconductor structure includes a base substrate including a semiconductor substrate having a PMOS region and an NMOS region and a plurality of fins on the semiconductor substrate, a gate layer across the plurality of fins by covering portions of top and sidewall surfaces of the fins, a P-type doped epitaxial layer formed in the fins at both sides of the gate layer in the PMOS region, an N-type doped epitaxial layer formed in the fins at both sides of the gate layer in the NMOS region, and an N-region mask layer formed on sidewall surfaces of the N-type doped epitaxial layer and covering the P-type doped epitaxial layer. A portion of the N-type doped epitaxial layer exposed by the N-region mask layer is processed by an N-type dopant segregated Schottky doping process.

A fin field effect transistor (Fin FET) device includes a fin structure extending in a first direction and protruding from an isolation insulating layer disposed over a substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.

An integrated circuit structure includes a semiconductor substrate having a plurality of semiconductor strips, a first recess being formed by two adjacent semiconductor strips among the plurality of semiconductor strips, a second recess being formed within the first recess, and an isolation region being provided in the first recess and the second recess. The second recess has a lower depth than the first recess.

A method of forming vertical transport field effect transistor (VTFET) devices is provided. The method includes forming a plurality of vertical fins on an upper insulating layer of a dual insulator layer semiconductor-on-insulator (SeOI) substrate, and forming two masking blocks on the plurality of vertical fins, wherein a portion of a protective layer and a fin template on each of the plurality of vertical fins is exposed between the two masking blocks. The method further includes removing a portion of the upper insulating layer between the two masking blocks to form a first cavity beneath the plurality of vertical fins, and forming a first bottom source/drain in the first cavity below the plurality of vertical fins. The method further includes replacing the two masking blocks with a masking layer patterned to have two mask openings above portions of the upper insulating layer adjacent to the first bottom source/drain.

A method includes providing a semiconductor structure including a first semiconductor substrate, an insulator layer over the first semiconductor substrate, and a second semiconductor substrate over the insulator layer; patterning the second semiconductor substrate to form a top fin portion over the insulator layer; conformally depositing a protection layer to cover the top fin portion, wherein a first portion of the protection layer is in contact with a top surface of the insulator layer; etching the protection layer to remove a second portion of the protection layer directly over the top fin portion while a third portion of the protection layer still covers a sidewall of the top fin portion; etching the insulator layer by using the third portion of the protection layer as an etch mask; and after etching the insulator layer, removing the third portion of the protection layer.

A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

A method for forming a semiconductor structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes depositing a dopant source layer over the gate structure. The method also includes driving dopants of the dopant source layer into the fin structure. The method also includes removing the dopant source layer. The method also includes annealing the dopants in the fin structure to form a doped region. The method also includes etching the doped region and the fin structure below the doped region to form a recess. The method also includes growing a source/drain feature in the recess.

Semiconductor structures and methods are provided. A semiconductor structure according to an embodiment includes a first cell disposed over a first well doped with a first-type dopant, a second cell disposed over the first well, and a tap cell disposed over the first well. The tap cell is sandwiched between the first cell and the second cell. The first cell includes a first plurality of transistors and the second cell includes a second plurality of transistors.

An integrated circuit (IC) chip is provided. In one aspect, a semiconductor substrate includes active devices on its front surface and power delivery tracks on its back surface. The active devices are powered through mutually parallel buried power rails, with the power delivery tracks running transversely with respect to the power rails, and connected to the power rails by a plurality of Through Semiconductor Via connections, which run from the power rails to the back of the substrate. The TSVs are elongate slit-shaped TSVs aligned to the power rails and arranged in a staggered pattern, so that any one of the power delivery tracks is connected to a first row of mutually parallel TSVs, and any power delivery track directly adjacent to the power delivery track is connected to another row of TSVs which are staggered relative to the TSVs of the first row. A method of producing an IC chip includes producing the slit-shaped TSVs before the buried power rails.