A physical layout of a symmetric FET is described which provides symmetry in voltages coupled to structures of the FET so to reduce OFF state asymmetry in capacitances generated by the structures when the FET is used as a switch. According to one aspect, the symmetric FET is divided into two halves that are electrically coupled in parallel. Gate structures of the two half FETs are arranged in the middle region of the layout, each gate structure having gate fingers that project towards opposite directions. Interdigitated source and drain structures run along the gate fingers and include crossover structures that cross source and drain structures in the middle region of the layout. The gate structures share a body contact region that is arranged in the middle of the layout between the two gate structures.

Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion (e.g. DC/DC) and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors. According to an aspect, timing control of edges of a control signal to the high voltage semiconductor devices is provided by a basic edge delay circuit that includes a transistor, a current source and a capacitor. An inverter can be selectively coupled, via a switch, to an input and/or an output of the basic edge delay circuit to allow for timing control of a rising edge or a falling edge of the control signal.

Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion (e.g. DC/DC) and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors. According to an aspect, timing control of edges of a control signal to the high voltage semiconductor devices is provided by a basic edge delay circuit that includes a transistor, a current source and a capacitor. An inverter can be selectively coupled, via a switch, to an input and/or an output of the basic edge delay circuit to allow for timing control of a rising edge or a falling edge of the control signal.

A physical layout of a symmetric FET is described which provides symmetry in voltages coupled to structures of the FET so to reduce OFF state asymmetry in capacitances generated by the structures when the FET is used as a switch. According to one aspect, the symmetric FET is divided into two halves that are electrically coupled in parallel. Gate structures of the two half FETs are arranged in the middle region of the layout, each gate structure having gate fingers that project towards opposite directions. Interdigitated source and drain structures run along the gate fingers and include crossover structures that cross source and drain structures in the middle region of the layout. The gate structures share a body contact region that is arranged in the middle of the layout between the two gate structures.

A nitride semiconductor device includes a first impurity layer made of an Al.sub.1-XGa.sub.XN (0<X1) based material and containing a first impurity with which a depth of an acceptor level from a valence band (E.sub.T-E.sub.V) is made not less than 0.3 eV but less than 0.6 eV, an electron transit layer formed on the first impurity layer, an electron supply layer formed on the electron transit layer, agate electrode formed on the electron transit layer, and a source electrode and a drain electrode formed such that the source electrode and the drain electrode sandwich the gate electrode and electrically connected to the electron supply layer.

The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer disposed on the substrate, a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer. The semiconductor device further includes a first gate conductor disposed on a first region of the second nitride semiconductor layer, a first source electrode disposed on a first side of the first gate conductor, a first field plate disposed on a second side of the first gate conductor; and a capacitor having a first conductive layer and a second conductive layer and disposed on a second region of the second nitride semiconductor layer. Wherein the first conductive layer of the capacitor and the first source electrode have a first material, and the second conductive layer of the capacitor and the first field plate have a second material.

The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer disposed on the substrate, a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer. The semiconductor device further includes a first gate conductor disposed on a first region of the second nitride semiconductor layer, a first source electrode disposed on a first side of the first gate conductor, a first field plate disposed on a second side of the first gate conductor; and a capacitor having a first conductive layer and a second conductive layer and disposed on a second region of the second nitride semiconductor layer. Wherein the first conductive layer of the capacitor and the first source electrode have a first material, and the second conductive layer of the capacitor and the first field plate have a second material.

A multi-layer wafer and method of manufacturing such wafer are provided. The method comprises applying a stress compensating oxide layer to each of two heterogeneous wafers, applying at least one bonding oxide layer to at least one of the two heterogeneous wafers, chemical-mechanical polishing the at least one bonding oxide layer, and low temperature bonding the two heterogeneous wafers to form a multi-layer wafer pair. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafers having a stress compensating oxide layer and at least one bonding oxide layer applied to at least one of the two heterogeneous wafers. The two heterogeneous wafers are low temperature bonded together to form the multi-layer wafer.

A multi-layer wafer and method of manufacturing such wafer are provided. The method comprises applying a stress compensating oxide layer to each of two heterogeneous wafers, applying at least one bonding oxide layer to at least one of the two heterogeneous wafers, chemical-mechanical polishing the at least one bonding oxide layer, and low temperature bonding the two heterogeneous wafers to form a multi-layer wafer pair. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafers having a stress compensating oxide layer and at least one bonding oxide layer applied to at least one of the two heterogeneous wafers. The two heterogeneous wafers are low temperature bonded together to form the multi-layer wafer.

A substrate 10 comprises: a first layer L1 containing crystalline aluminum nitride; a second layer L2 containing crystalline -alumina; and an intermediate layer Lm sandwiched between the first layer L1 and the second layer L2 and containing aluminum, nitrogen, and oxygen, and the content of nitrogen in the intermediate layer Lm decreases in a direction Z from the first layer L1 toward the second layer L2, and the content of oxygen in the intermediate layer Lm increases in the direction Z from the first layer L1 toward the second layer L2.