Embodiments are directed to a method and resulting structures for forming thin and thick gate dielectric nanosheet transistors on the same chip. A first nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on a substrate. A second nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on the substrate. The first nanosheet of the first nanosheet stack is doped and concurrently removed with the first sacrificial layer of the first nanosheet stack and the first sacrificial layer of the second nanosheet stack.

Embodiments are directed to a method and resulting structures for forming thin and thick gate dielectric nanosheet transistors on the same chip. A first nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on a substrate. A second nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on the substrate. The first nanosheet of the first nanosheet stack is doped and concurrently removed with the first sacrificial layer of the first nanosheet stack and the first sacrificial layer of the second nanosheet stack.

A handle substrate of a composite substrate for a semiconductor includes a base substrate comprising a polycrystalline material; and an amorphous layer provided over the base substrate, the amorphous layer having chemical resistance and comprising a single component with a high purity.

A handle substrate of a composite substrate for a semiconductor includes a base substrate comprising a polycrystalline material; and an amorphous layer provided over the base substrate, the amorphous layer having chemical resistance and comprising a single component with a high purity.

A composite substrate includes a single crystal support substrate containing first element as a main component; an oxide single crystal layer provided on the single crystal support substrate and containing a second element (excluding oxygen) as a main component; and an amorphous layer provided in between the single crystal support substrate and the oxide single crystal layer and containing a first element, a second element, and Ar, the amorphous layer having a first amorphous region in which proportion of the first element is higher than proportion of the second element, and a second amorphous region in which the proportion of the second element is higher than the proportion of the first element, concentration of Ar contained in the first amorphous region being higher than concentration of Ar contained in the second amorphous region and being 3 atom % or more.

IC device structures including a lateral compound resistor disposed over a surface of a substrate, and fabrication techniques to form such a resistor in conjunction with fabrication of a transistor. Rather than being stacked vertically, a compound resistive trace may include a plurality of resistive materials arranged laterally over a substrate. Along a resistive trace length, a first resistive material is in contact with a sidewall of a second resistive material. A portion of a first resistive material along a centerline of the resistive trace may be replaced with a second resistive material so that the second resistive material is embedded within the first resistive material.

IC device structures including a lateral compound resistor disposed over a surface of a substrate, and fabrication techniques to form such a resistor in conjunction with fabrication of a transistor. Rather than being stacked vertically, a compound resistive trace may include a plurality of resistive materials arranged laterally over a substrate. Along a resistive trace length, a first resistive material is in contact with a sidewall of a second resistive material. A portion of a first resistive material along a centerline of the resistive trace may be replaced with a second resistive material so that the second resistive material is embedded within the first resistive material.

A FET based double balanced mixer (DBM) that exhibits good conversion gain and IIP3 values and provides improved linearity and wide bandwidth. In one embodiment, a first balun is configured to receive a local oscillator (LO) signal and generate two balanced LO signals that are coupled to two corresponding opposing nodes of a four-node FET ring. A second balun is configured to pass an RF signal on the unbalanced side. The FET ring includes at least four FETs connected as branches of a ring, with the source of each FET connected to the drain of a next FET in the ring. Each FET is preferably fabricated as, or configured as, a low threshold voltage device having its gate connected to its drain, which causes the FET to operate as a diode, but with the unique characteristic of having close to a zero turn-on voltage.

Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion (e.g. DC/DC) and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors. A parallel resistive-capacitive coupling allows transmission of edge information and DC level information of control signals from a static voltage domain to a flying voltage domain. A flying comparator operating in the flying voltage domain uses clamps to force an output difference voltage that is zero only during a switching event of the flying voltage domain. A charge pump may be used to amplify inputs to the parallel-resistive coupling for a desired differential signal amplitude to the flying comparator.

Embodiments are directed to a method and resulting structures for forming thin and thick gate dielectric nanosheet transistors on the same chip. A first nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on a substrate. A second nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on the substrate. The first nanosheet of the first nanosheet stack is doped and concurrently removed with the first sacrificial layer of the first nanosheet stack and the first sacrificial layer of the second nanosheet stack.