The present disclosure provides a diode-triggered bidirectional silicon controlled rectifier and circuit. The silicon controlled rectifier includes: a P-type substrate; a first P well formed in the P-type substrate, a first P-type doped region and a first N-type doped region being formed in the first P well; a second P well formed in the P-type substrate, a third N-type doped region and a fourth P-type doped region being formed in the second P well; and an N well formed in the P-type substrate, a second P-type doped region, a second N-type doped region and a third P-type doped region being formed in the N well. The second N-type doped region is electrically connected with a positive electrode of a diode string, and the first P-type doped region and the fourth P-type doped region are electrically connected with a negative electrode of the diode string.

The present disclosure relates to the technical field of semiconductors, and provides an electro-static discharge (ESD) protection structure and a chip. The ESD protection structure includes: a semiconductor substrate, a first P-type well, a first N-type well, a first N-type doped portion, a first P-type doped portion, a second N-type doped portion, a second P-type doped portion, a third doped well, a third P-type doped portion and a third N-type doped portion, wherein the first P-type well, the first N-type well and the third doped well are located in the semiconductor substrate; the first N-type doped portion and the first P-type doped portion are located in the first N-type well and spaced apart; the second N-type doped portion and the second P-type doped portion are located in the first P-type well and spaced apart.

The present disclosure provides an electrostatic discharge protection device, and relates to the technical field of semiconductors. A first P-type heavily-doped region and a first N-type heavily-doped region of the electrostatic discharge protection device are located in a P well, a second P-type heavily-doped region and a third N-type heavily-doped region are located in a first N well, one part of a second N-type heavily-doped region is located in the P well, the other part is located in the first N well, and the P well and the first N well are located in a P-type substrate. The P-type substrate is provided with a gate structure, the gate structure, the first N-type heavily-doped region, and the second N-type heavily-doped region form a transistor, the first N-type heavily-doped region and the gate structure are connected to a first voltage.

An electro-static discharge protection circuit and a semiconductor device are provided. The electro-static discharge protection circuit includes: an electro-static discharge path including a Silicon Controlled Rectifier (SCR) connected between a first potential terminal and a second potential terminal; a Negative channel-Metal-Oxide-Semiconductor (NMOS) transistor connected to the SCR and configured to be turned on by an electro-static voltage, to trigger the SCR to be turned on; and a first resistance connected in parallel with at least part of the electro-static discharge path and configured to shunt a current of the electro-static discharge path when the SCR is turned on.

Embodiments of the present application provide an electro-static discharge protection circuit and a chip. The electro-static discharge protection circuit includes: a silicon-controlled rectifier, including an anode, a cathode and an electro-static discharge path; a detection unit, connected between the anode and the cathode of the silicon-controlled rectifier, and configured to generate a trigger signal in response to static electricity occurring in a protected chip; and a switching unit, connected to the electro-static discharge path, including an input terminal connected to an output terminal of the detection unit, and configured to turn on the electro-static discharge path based on the trigger signal to discharge an electro-static discharge current.

An electrostatic discharge (ESD), protection device is provided. In accordance with the present disclosure, an ESD protection device is provided that includes a series connection of a first unit having strong snapback and low series capacitance and a second high-voltage unit that displays a relatively high holding/trigger voltage to ensure latch up and improper triggering of the ESD protection device while at the same time providing high-voltage operation with low capacitive loading.

A bidirectional electrostatic discharge protection device includes at least one bipolar junction transistor and at least one silicon-controlled rectifier. The silicon-controlled rectifier is coupled to the bipolar junction transistor in series. The absolute value of the breakdown voltage of the bipolar junction transistor is lower than that of the silicon-controlled rectifier and the absolute value of the holding voltage of the bipolar junction transistor is higher than that of the silicon-controlled rectifier when an electrostatic discharge voltage is applied to the bipolar junction transistor and the silicon-controlled rectifier.

A multi-channel transient voltage suppression device includes a semiconductor substrate, a semiconductor layer, at least two bidirectional transient voltage suppression structures, and at least one isolation trench. The semiconductor substrate, having a first conductivity type, is coupled to a grounding terminal. The semiconductor layer, having a second conductivity type opposite to the first conductivity type, is formed on the semiconductor substrate. The bidirectional transient voltage suppression structures are formed in the semiconductor layer. Each bidirectional transient voltage suppression structure is coupled to an input/output (I/O) pin and the grounding terminal. The isolation trench is formed in the semiconductor substrate and the semiconductor layer and formed between the bidirectional transient voltage suppression structures. The isolation trench has a height larger than the height of the semiconductor layer and surrounds the bidirectional transient voltage suppression structures.

An electrostatic protection circuit connected with an internal circuit is provided. The electrostatic protection circuit includes: a first circuit, a first diode connected in parallel with the first circuit, a second circuit, and a second diode connected in parallel with the second circuit. The first circuit is connected between a power supply pad and an internal circuit input terminal. The second circuit is connected between the internal circuit input terminal and a ground pad. The first circuit and the second circuit are diode-triggered silicon controlled rectifier circuits. The technical solution of the disclosure can improve electrostatic protection capability of a charged device model of a chip.

An ESD clamp circuit has an ESD detection circuit connected between a first terminal and a second terminal, with a first output node and a second output node. The ESD detection circuit is configured to output respective first and second control signals at the first and second output nodes in response to an ESD event. A discharge circuit includes a p-type transistor having a source, a drain and a gate, with the gate connected to the first output node. An n-type transistor has a source, a drain and a gate, with the gate connected to the second output node. The drain is connected to the drain of the p-type transistor. The discharge circuit is configured to establish a first ESD discharge path from the first terminal, through the p-type transistor and the n-type transistor, to the second terminal, and to further establish a second ESD discharge path in parallel with the first ESD discharge path. The second ESD discharge path includes a parasitic silicon controlled rectifier (SCR).