An ESD protection structure formed within a semiconductor substrate of an integrated circuit device. The ESD protection structure comprises a thyristor structure being formed from a first P-doped section forming an anode of the thyristor structure, a first N-doped section forming a collector node of the thyristor structure, a second P-doped section, and a second N-doped section forming a cathode of the thyristor structure. A low-resistance coupling is provided between an upper surface region of the collector node of the thyristor structure and the anode of the thyristor structure.

The present disclosure relates to an electrostatic protection device including an SCR and a manufacturing method thereof. The electrostatic protection device includes a third N+ doped region across an N-type well region and a P-type well region, and a third P+ doped region adjacent to the third N+ doped region. Each of the third N+ doped region and the third P+ doped region has a high doping concentration. In a case that Zener breakdown occurs in a PN junction structure between the third N+ doped region and the third P+ doped region, the SCR is triggered to form a discharge current path. The present disclosure can reduce a trigger voltage of an electrostatic protection device including an SCR, and can provide electrostatic protection devices having different trigger voltages, with high stability and high robustness.

IC devices including IC devices including BPRs that form metal-semiconductor junctions with semiconductor sections where the BPRs are partially buried are disclosed. An example IC device includes a first layer comprising semiconductor structures, such as fins, nanowires, or nanoribbons. The IC device also includes a layer comprising an electrically conductive material and coupled to the semiconductor structures. The IC device further includes a support structure comprising a BPR and a semiconductor section. The BPR contacts with the semiconductor section and forms a metal-semiconductor junction. The metal-semiconductor junction constitutes a Schottky barrier for electrons. The IC device may include a SCR including a sequence of p-well, n-well, p-well, and n-well with Schottky barriers in the first p-well and the second n-well. The Schottky barrier may also be used as a guard ring to extract injected charge carriers.

Apparatus and methods for actively-controlled trigger and latch release thyristor are provided. In certain configurations, an actively-controlled protection circuit includes an overvoltage sense circuit, a thyristor or silicon controlled rectifier (SCR) that is electrically connected between a signal node and a discharge node, and an active trigger and latch release circuit. The overvoltage sense circuit controls a voltage of a dummy supply node based on a voltage of the signal node, and the active trigger and latch release circuit detects presence of a transient overstress event at the signal node based on the voltage of the dummy supply node. The active trigger and latch release circuit provides one or more trigger signals to the SCR to control the SCR's activation voltage, and the active trigger and latch release circuit activates or deactivates the one or more trigger signals based on whether or not the transient overstress event is detected.

A semiconductor device includes a substrate having a semiconductor surface doped a second dopant type with a buried layer (BL) doped a first dopant type. First, second and third well regions doped the second dopant type are on top of the BL. Second doped regions doped the first dopant type on top of and contacting the BL arraigned as a first well ring and second well ring are around the first and third well regions respectively. At least one high-injection component including the first well region is surrounded by the first well ring. At least one component including the third well region is surrounded by the second well ring. An npn or pnp guard wall pocket including a wall of the first and second well rings, and the second well region is between the high-injection component and the component.

Disclosed are embodiments of a semiconductor structure that includes a semiconductor-controlled rectifier (e.g., for electrostatic discharge (ESD) protection). The SCR can be readily integrated into advanced semiconductor-on-insulator processing technology platforms (e.g., a fully depleted silicon-on-insulator (FDSOI) processing technology platform) that employ hybrid semiconductor substrates (i.e., semiconductor substrates with both bulk semiconductor and semiconductor-on-insulator regions) and is configured with an on-Pwell semiconductor-on-insulator gate structure that is tied to an anode terminal to effectively lower the SCR trigger voltage. To further lower the trigger voltage of the SCR, the Pwell on which the gate structure sits may be made narrower than the gate structure and/or the doping profile of the Pwell on which the gate structure sits may be graded (e.g., P to P- closer to insulator layer). Additionally, to minimize parasitic capacitance, the gate structure may be shorter in length than contact regions parallel and adjacent thereto.

A chip includes a first die, a second die, a first and a second through-silicon vias, a first protection circuit, and a second protection circuit. The first die has a first operational voltage node and a first reference voltage node. The second die has a second operational voltage node and a second reference voltage node. The first and the second through-silicon vias are configured to couple the first die and the second die. The first protection circuit is coupled between the first operational voltage node and the first through-silicon via. The second protection circuit is coupled between the first reference voltage node and the second through-silicon via. The first through-silicon via is further coupled to the second reference voltage node or the second operational voltage node. The second through-silicon via is further coupled to the first reference voltage node or the first operational voltage node.

The disclosure relates to a data transmission system (100) comprising a signal line (101) and a ground line (103). A first signal path (102) is provided between the signal line (101) and the ground line (103). The first signal path (102) comprises a Shockley diode (104) having a cathode (106) and an anode (108). The cathode (106) is connected to the ground line (103) and the anode (108) is connected to the signal line (101).

An electro-static protection circuit and a chip are provided. The electro-static protection circuit includes an electro-static protection circuit and a control circuit. The electro-static protection circuit is located inside a protected chip and connected with the protected circuit. The control circuit is connected with the electro-static protection circuit, and is configured to output a high-level signal to the electro-static protection circuit to trigger the electro-static protection circuit to discharge an electro-static current when static electricity is generated on the protected chip, and output a low-level signal to the electro-static protection circuit to reduce a static leakage current of the electro-static protection circuit when the static electricity is not generated on the protected chip.

A semiconductor device and a corresponding circuit for shunting current in a circuit protection configuration is disclosed. An example device includes a first semiconductor region having an anode electrical contact, a second semiconductor region having a cathode electrical contact, a third semiconductor region extending between the first semiconductor region and the second semiconductor region, the second semiconductor region and the third semiconductor region forming a PN junction therebetween, and a gate coupled to the third semiconductor region. The gate is controllable between a first mode in which additional space charges are induced in the semiconductor region to deplete the semiconductor region, and a second mode in which additional space charges are not induced in the semiconductor region.