A mother substrate and a display panel are disclosed. The mother substrate includes a plurality of display panels, a plurality of first test terminals and a plurality of first one-way conductive circuits. Each of the display panels has a display area, and includes a plurality of first signal lines extending from outside of the display area to the display area in parallel; the plurality of first signal lines of each of the display panels are respectively electrically connected to one of the plurality of first test terminals; the plurality of first one-way conductive circuits are respectively electrically connected to the plurality of first signal lines outside the display area and are configured to allow signals to be able to transmit only from the plurality of first test terminals to the plurality of first signal lines of each of the display panels.

An apparatus for electrostatic discharge protection. In one embodiment, an integrated circuit (IC) includes a trigger circuit configured to generate a trigger voltage VT in response to an electrostatic discharge (ESD) event. A plurality of metal oxide semiconductor (MOS) transistors are coupled to the trigger circuit. The plurality of MOS transistors are configured to conduct ESD current from a plurality of circuit nodes, respectively, to a ground conductor in response to the trigger circuit generating the trigger voltage VT. A voltage limiter circuit is also included and is configured to limit the trigger voltage VT.

A static electricity prevention circuit of a display device including: a driving circuit configured to drive a display unit that displays an image, at least one clock signal wire configured to transmit a clock signal to the driving circuit, at least one transistor electrically coupled to the clock signal wire, and at least one capacitor including a first electrode coupled to a source electrode and to a drain electrode of the transistor, and a second electrode configured to be maintained at a voltage.

A circuit includes an output and a reverse direction high-electron-mobility transistor. The reverse direction high-electron-mobility transistor includes a drain connected to the output. The reverse direction high-electron-mobility transistor also includes a source and a gate. A transistor includes a source, a gate connected to a control pin and a drain connected to the gate of the reverse direction high-electron-mobility transistor.

A flip-flop circuit includes two inverters and two transmission circuits. The two inverters and the two transmission circuits are implemented using reverse direction high-electron-mobility transistors.

An apparatus for electrostatic discharge protection. In one embodiment, an integrated circuit (IC) includes a trigger circuit configured to generate a trigger voltage VT in response to an electrostatic discharge (ESD) event. A plurality of metal oxide semiconductor (MOS) transistors are coupled to the trigger circuit. The plurality of MOS transistors are configured to conduct ESD current from a plurality of circuit nodes, respectively, to a ground conductor in response to the trigger circuit generating the trigger voltage VT. A voltage limiter circuit is also included and is configured to limit the trigger voltage VT.

An integrated circuit device with ESD protection includes a substrate with a well having a first conductivity type formed on the substrate. A drain region has at least one drain diffusion with a second conductivity type implanted in the well and at least one drain conductive insertion on the well. The drain conductive insertion is electrically connected to the drain diffusion and an I/O pad. A source region includes a plurality of source diffusions having the second conductivity type implanted in the well, and the source diffusions are electrically connected to a voltage terminal.

A semiconductor device contains a Zener-triggered transistor having a Zener diode vertically integrated in a first current node of the Zener-triggered transistor. The first current node includes an n-type semiconductor material contacting a p-type semiconductor material in a substrate. The Zener diode includes an n-type cathode contacting the first current node, and a p-type anode contacting the n-type cathode and contacting the p-type semiconductor material. The semiconductor device may be formed using an implant mask, with an opening for the Zener diode. Boron and arsenic are implanted into the substrate in an area exposed by the opening in the implant mask. The substrate is subsequently heated to diffuse and activate the implanted boron and arsenic. The Zener-triggered transistor may be used in an ESD circuit or a snubber circuit.

Protection against electrostatic discharges is to be improved for electronic devices, or is to be provided in the first place. The device for protection against electrostatic discharges having an integrated semiconductor protection device comprises an inner region (1) configured at least as a thyristor (SCR) and at least one outer region (2a, 2b) configured as a corner region, which is formed and configured at least as a PNP transistor. The inner region (1) and the at least one outer region (2a, 2b) are arranged adjacent to one another.

An electrostatic discharge (ESD) protection device and a method thereof are presented. A well is disposed in a substrate. A gate is disposed on the well. A source region and a drain region are located in the well and at two opposite sides of the gate respectively. A first doped region is located in the drain region, wherein the first doped region is electrically connected to the drain region. A second doped region is located in the source region, wherein the second doped region is electrically connected to the source region. A third doped region is located in the well and at a side of the drain region opposite to the gate. A fourth doped region is located in the well and at a side of the source region opposite to the gate, wherein the fourth doped region is electrically connected to the third doped region.